The for_each_child_of_node macro itself maintains the correct reference
count of the nodes so the explicit of_node_put() call causes a warning:

[    0.098960] OF: ERROR: Bad of_node_put() on /pmc@7000e400/powergates/xusba
[    0.098981] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.3 #1-NixOS
[    0.098996] Hardware name: NVIDIA Jetson TX1 Developer Kit (DT)
[    0.099011] Call trace:
[    0.099034] [<ffff00000808a048>] dump_backtrace+0x0/0x2a0
[    0.099051] [<ffff00000808a30c>] show_stack+0x24/0x30
[    0.099069] [<ffff0000084a6494>] dump_stack+0x9c/0xc0
[    0.099090] [<ffff000008992214>] of_node_release+0xa4/0xa8
[    0.099107] [<ffff0000084a9270>] kobject_put+0x90/0x1f8
[    0.099124] [<ffff0000089914ac>] of_node_put+0x24/0x30
[    0.099140] [<ffff00000898cec4>] __of_get_next_child+0x4c/0x70
[    0.099155] [<ffff00000898cf28>] of_get_next_child+0x40/0x68
[    0.099173] [<ffff0000090a099c>] tegra_pmc_early_init+0x4e8/0x5ac
[    0.099189] [<ffff00000808399c>] do_one_initcall+0x5c/0x168
[    0.099206] [<ffff000009050c98>] kernel_init_freeable+0xd4/0x240
[    0.099224] [<ffff000008b2d658>] kernel_init+0x18/0x108
[    0.099238] [<ffff0000080836c0>] ret_from_fork+0x10/0x50

(It's not very apparent from the OF documentation that of_node_put() is
not needed; the macro itself has no docstring and of_get_next_child()
used in the implementation begins with "Returns a node pointer with
refcount incremented" but then only at the very end of the docstring
the crucial part "Decrements the refcount of prev" is mentioned.)

Fixes: a3804512 ("soc/tegra: pmc: Add generic PM domain support")
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The various error messages refer to the PM domains as "power domain",
"genpd" and "PM domain". That's confusing, so convert all error messages
to use the most prominent: "PM domain".
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 3fe57710 ("PM / Domains: Add support for removing PM
domains") add support for removing PM domains. Update the Tegra PMC
driver to remove PM domains if we fail to add a provider for the PM
domain.

Please note that the code under 'power_on_cleanup' label does not
really belong in the clean-up error path for tegra_powergate_add().
To keep the error path simple, remove this label and move the
associated code to where it needs to be invoked.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 7eb231c3 ("PM / Domains: Convert pm_genpd_init() to return
an error code") updated pm_genpd_init() to return an error code. Update
the Tegra PMC driver to check the return value from pm_genpd_init() and
handle any errors returned.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: use pr_err() instead of dev_err()]
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use pr_err() instead of dev_err() when the pmc->dev field has not been
initialized yet and add a few missing error messages as well as remove
duplicate ones.

Based on work by Jon Hunter <jonathanh@nvidia.com>.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_io_rail_prepare() converts the IO rail ID into a
bit position that is used to check the status and control the IO rail
in the PMC registers. However, rather than converting to a bit position
it is more useful to convert to a bit-mask because this is what is
actually used. By doing so the BIT() marco only needs to be used once
and we can use the IO_DPD_REQ_CODE_MASK when checking for erroneous rail
IDs.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: rebase and rename bit -> mask]
Signed-off-by: NThierry Reding <treding@nvidia.com>

It is possible for the public functions, tegra_io_rail_power_on/off()
to be called before the PMC device has been probed. If this happens
then the pmc->clk member will not be initialised and the call to
clk_get_rate() in tegra_io_rail_prepare() will return zero and lead
to a divide-by-zero exception. The function clk_get_rate() will return
zero if a NULl clk pointer is passed. Therefore, rather that checking
if pmc->clk is initialised, fix this by checking the return value for
clk_get_rate() to make sure it is not zero.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such
pad can be used to control the common voltage signal level and power
state of the pins in the given pad.

I/O pads can be powered down even if the system is active, which can
save power from that I/O interface. For SoC generations prior to
Tegra124 the I/O pad voltage is automatically detected and hence the
system software doesn't need to configure it. However, starting with
Tegra210 the detection logic has been removed, so explicit control of
the I/O pad voltage by system software is required.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Bit definitions are sorted in decreasing order by offset. Apply the same
ordering to all definitions.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Reading the DPD_REQ & DPD2_REQ registers returns the previous requests.
If we sets the current request bit with the returned value, then other
pads will be turned on or off unexpectedly.
Signed-off-by: NVince Hsu <vinceh@nvidia.com>
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra XHCI driver does not currently manage the Tegra XUSB power
partitions and so it these partitions have not been enabled by the
bootloader then the system will crash when probing the XHCI device.

While proper support for managing the power partitions is being
developed to the XHCI driver for Tegra, for now power on all the XUSB
partitions for USB host and super-speed on boot if the XHCI driver is
enabled.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

If CONFIG_PM_GENERIC_DOMAINS is not enabled, then power partitions
associated with a device will not be enabled automatically by the PM
core when the device is in use. To avoid situations where a device in
a power partition is to be used but the partition is not enabled,
initialise the power partitions for Tegra early in the boot process and
if CONFIG_PM_GENERIC_DOMAINS is not enabled, then power on all
partitions defined in the device-tree blob.

Note that if CONFIG_PM_GENERIC_DOMAINS is not enabled, after the
partitions are turned on, the clocks and resets used as part of the
sequence for turning on the partition are released again as they are no
longer needed by the PMC driver. Another benefit of this is that this
avoids any issues of sharing resets between the PMC driver and other
device drivers that may wish to independently control a particular
reset.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

When initialising a powergate, only a single error message is shown if
the initialisation fails. Add more error messages to give specific
details of what failed if the initialisation failed and remove the
generic failure message.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use blank lines after blocks and before labels for consistency with the
existing code in the file.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 0259f522 ('soc/tegra: pmc: Restore base address on probe
failure') fixes an issue where the PMC base address pointer is not
restored on probe failure. However, this fix creates another problem
where if early initialisation of the PMC driver fails and an initial
mapping for the PMC address space is not created, then when the PMC
device is probed, the PMC base address pointer will not be valid and
this will cause a crash when tegra_pmc_init() is called and attempts
to access a register.

Although the PMC address space is mapped a 2nd time during the probe
and so this could be fixed by populating the base address pointer
earlier during the probe, this adds more complexity to the code.
Moreover, the PMC probe also assumes the the soc data pointer is also
initialised when the device is probed and if not will also lead to a
crash when calling tegra_pmc_init_tsense_reset(). Given that if the
early initialisation does fail then something bad has happen, it seems
acceptable to allow the PMC device probe to fail as well. Therefore, if
the PMC base address pointer or soc data pointer are not valid when
probing the PMC device, WARN and return an error.

Fixes: 0259f522 ('soc/tegra: pmc: Restore base address on probe failure')
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add missing of_node_put() in PMC early initialisation function to avoid
leaking the device nodes.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: squash in a couple more of_node_put() calls]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The mutex used by the PMC driver may not be initialised if early
initialisation of the driver fails. If this does happen, then it could
be possible for callers of the public PMC functions to still attempt to
acquire the mutex. Fix this by initialising the mutex as soon as
possible to ensure it will always be initialised.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The public functions exported by the PMC driver use the presence of the
SoC data pointer to determine if the PMC device is configured and the
registers can be accessed. However, the SoC data is populated before the
PMC register space is mapped and this opens a window where the SoC data
pointer is valid but the register space has not yet been mapped which
could lead to a crash. Furthermore, if the mapping of the PMC register
space fails, then the SoC data pointer is not cleared and so would
expose a larger window where a crash could occur.

Fix this by initialising the SoC data pointer after the PMC register
space has been mapped.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

During early initialisation, the available power partitions for a given
device is configured as well as the polarity of the PMC interrupt. Both
of which should only be configured if there is a valid device node for
the PMC device. This is because the soc data used for configuring the
power partitions is only available if a device node for the PMC is found
and the code to configure the interrupt polarity uses the device node
pointer directly.

Some early device-tree images may not have this device node and so fix
this by ensuring the device node pointer is valid when configuring these
items.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_power_sequence_power_up() is a public function used
to power on a partition. When this function is called, we do not check
to see if the partition being powered up is valid/available. Fix this
by checking to see that the partition is valid/available.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

When registering the Tegra power partitions with the generic PM domain
framework, the current state of the each partition is checked and used
as the default state for the partition. However, the state of each reset
associated with the partition is not initialised and so it is possible
that the state of the resets are not in the expected state. For example,
if a partition is on, then the resets should be de-asserted and if the
partition is off, the resets should be asserted.

There have been cases where the bootloader has powered on a partition
and only de-asserted some of the resets to some of the devices in the
partition. This can cause accesses to these devices to hang the system
when the kernel boots and attempts to probe these devices.

Ideally, the driver for the device should ensure the reset has been
de-asserted when probing, but the resets cannot be shared between the
PMC driver (that needs to de-assert/assert the reset when turning the
partition on or off) and another driver because we cannot ensure the
reset is in the correct state.

To ensure the resets are in the correct state, when using the generic
PM domain framework, put each reset associated with the partition in
the correct state (based upon the partition's current state) when
obtaining the resets for a partition.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use register definitions for the main SoC reset operation instead of
hard-coding magic values. Note that the PMC_RST_STATUS register isn't
actually accessed, but since it is mentioned in a comment the
definitions are added for completeness.
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Adds generic PM domain support to the PMC driver where the PM domains
are populated from device-tree and the PM domain consumer devices are
bound to their relevant PM domains via device-tree as well.

Update the tegra_powergate_sequence_power_up() API so that internally
it calls the same tegra_powergate_xxx functions that are used by the
Tegra generic PM domain code for consistency.

To ensure that the Tegra power domains (a.k.a. powergates) cannot be
controlled via both the legacy tegra_powergate_xxx functions as well
as the generic PM domain framework, add a bit map for available
powergates that can be controlled via the legacy powergate functions.

Move the majority of the tegra_powergate_remove_clamping() function
to a sub-function, so that this can be used by both the legacy and
generic power domain code.

This is based upon work by Thierry Reding <treding@nvidia.com>
and Vince Hsu <vinceh@nvidia.com>.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Currently, the function tegra_powergate_set() simply sets the desired
powergate state but does not wait for the state to change. In most cases
we should wait for the state to change before proceeding. Currently,
there is a case for Tegra114 and Tegra124 devices where we do not wait
when starting the secondary CPU as this is not necessary. However, this
is only done at boot time and so waiting here will only have a small
impact on boot time. Therefore, update tegra_powergate_set() to wait
when setting the powergate.

By adding this feature, we can also eliminate the polling loop from
tegra30_boot_secondary().

A function has been added for checking the status of the powergate and
so update the tegra_powergate_is_powered() to use this macro as well.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

For Tegra124 and Tegra210, the GPU partition cannot be toggled on and
off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the
partition is simply powered up and down via an external regulator.
For these devices, there is a separate register for controlling the
signal clamping of the partition and this is described in the PMC SoC
data by the "has_gpu_clamp" variable. Use this variable to determine if
the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0
register and ensure that no one can incorrectly try to toggle the GPU
partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register.

Furthermore, we cannot use the APBDEV_PMC_PWRGATE_STATUS_0 register to
determine if the GPU partition is powered for Tegra124 and Tegra210.
However, if the GPU partition is powered, then the signal clamp for the
GPU partition should be removed and so use bit 0 of the
APBDEV_PMC_GPU_RG_CNTRL_0 register to determine if the clamp has been
removed (bit[0] = 0) and the GPU partition is powered.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_powergate_is_powered() verifies that the partition
being queried is valid and so there is no need to check this before
calling tegra_powergate_is_powered() in powergate_show(). So remove this
extra check.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra power partitions are referenced by numerical IDs which are the
same values programmed into the PMC registers for controlling the
partition. For a given device, the valid partition IDs may not be
contiguous and so simply checking that an ID is not greater than the
maximum ID supported may not mean it is valid. Fix this by checking if
the powergate is defined in the list of powergates for the Tegra SoC.

Add a helper function for checking valid powergates and use where we
need to verify if the powergate ID is valid or not.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

In tegra_powergate_set() the state of the powergates is read and OR'ed
with the bit for the powergate of interest. This unsigned 32-bit value
is then compared with a boolean value to test if the powergate is
already in the desired state. When turning on a powergate, apart from
the powergate that is represented by bit 0, this test will always
return false and so we may attempt to turn on the powergate when it is
already on.

After OR'ing the bit for the powergate, check if the result is not equal
to zero before comparing with the boolean value. Add a helper function
to return the current state of a powergate and use this in both
tegra_powergate_set() and tegra_powergate_is_powered() where we check
the powergate status.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra powergate and rail IDs are always positive values and so change
the type to be unsigned and remove the tests to see if the ID is less
than zero. Update the Tegra DC powergate type to be an unsigned as well.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The PMC base address pointer is initialised during early boot so that
early platform code may used the PMC public functions. During the probe
of the PMC driver the base address pointer is mapped again and the initial
mapping is freed. This exposes a window where a device accessing the PMC
registers via one of the public functions, could race with the updating
of the pointer and lead to a invalid access. Furthermore, the only
protection between multiple devices attempting to access the PMC registers
is when setting the powergate state to on or off. None of the other public
functions that access the PMC registers are protected.

Use the existing mutex to protect paths that may race with regard to
accessing the PMC registers.

Note that functions tegra_io_rail_prepare()/poll() either return a
negative value on failure or zero on success. Therefore, it is not
necessary to check if the return value is less than zero and so only
test that the return value is not zero to test for failure. This
simplifies the error handling with the mutex locking in place.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

During early initialisation, the PMC registers are mapped and the PMC SoC
data is populated in the PMC data structure. This allows other drivers
access the PMC register space, via the public Tegra PMC APIs, prior to
probing the PMC device.

When the PMC device is probed, the PMC registers are mapped again and if
successful the initial mapping is freed. If the probing of the PMC device
fails after the registers are remapped, then the registers will be
unmapped and hence the pointer to the PMC registers will be invalid. This
could lead to a potential crash, because once the PMC SoC data pointer is
populated, the driver assumes that the PMC register mapping is also valid
and a user calling any of the public Tegra PMC APIs could trigger an
exception because these APIs don't check that the mapping is still valid.

Fix this by updating the mapping and freeing the original mapping only if
probing the PMC device is successful.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra124 does not have an L2 power partition and the L2 cache is part of
the cluster 0 non-CPU (CONC) partition. Remove the L2 as a valid
partition for Tegra124. The TRM also shows that there is no L2 partition
for Tegra124.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The power partitions L2, HEG, CELP and C1NC do not exist on Tegra210 but
were incorrectly documented in the TRM. These will be removed from the
TRM and so also remove their definitions.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The debugfs entry for the PMC device will not be removed if the probe of
the device fails to register the restart handler. This leaves behind the
dangling debugfs entry with no driver backing it. Remove the entry to
avoid this.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Sparse reports the following warning for tegra_pmc_init_tsense_reset():

drivers/soc/tegra/pmc.c:741:6: warning: symbol 'tegra_pmc_init_tsense_reset' was not declared. Should it be static?

This function is only used internally by the PMC driver and so fix this
by making it static.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some members of the tegra_pmc structure are missing from the kernel-doc
comment for this structure. Add the missing members.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The driver requests the pclk clock at probe time already and stores its
reference to it in struct tegra_pmc, so there is no need to look it up
everytime it is needed. Use the existing reference instead.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Functions returning no value don't need an explicit return statement.
Signed-off-by: NThierry Reding <treding@nvidia.com>