1. 09 12月, 2014 2 次提交
    • S
      dma: cppi41: wait longer for the HW to return the descriptor · 6f9d7056
      Sebastian Andrzej Siewior 提交于
      For a "complete" teardown we have to wait until the teardown descriptor
      is returned by the hardware. The g_zero testcase "testusb -a -t 9" triggers
      the following warning quite reliable:
      
      |------------[ cut here ]------------
      |WARNING: CPU: 0 PID: 0 at drivers/dma/cppi41.c:609 cppi41_dma_control+0x198/0x304()
      |[<c003f84c>] (warn_slowpath_null) from [<c02be8d8>]
      |[<c02be8d8>] (cppi41_dma_control) from [<bf08d25c>]
      |[<bf08d25c>] (cppi41_dma_channel_abort [musb_hdrc])
      |[<bf08bc38>] (nuke.constprop.10 [musb_hdrc])
      |[<bf08bd08>] (musb_gadget_disable [musb_hdrc])
      |[<bf252524>] (disable_endpoints [usb_f_ss_lb])
      |[<bf2525d8>] (disable_source_sink [usb_f_ss_lb])
      |[<bf25260c>] (sourcesink_set_alt [usb_f_ss_lb])
      |[<bf23ad24>] (composite_setup [libcomposite])
      |[<bf08a2f4>] (musb_g_ep0_irq [musb_hdrc])
      |[<bf085ec4>] (musb_interrupt [musb_hdrc])
      |[<bf0aeaf4>] (dsps_interrupt [musb_dsps])
      |[<c0080ea8>] (handle_irq_event_percpu)
      |[<c008112c>] (handle_irq_event)
      |[<c008348c>] (handle_level_irq)
      |[<c00807a8>] (generic_handle_irq)
      |[<c000ee80>] (handle_IRQ)
      |[<c00085f0>] (omap3_intc_handle_irq)
      
      and complains about a TD descriptor which is not returned. I've been
      looking at several things and haven't noticed anything unusual that
      might lead to this.
      The manual says "to try again" until the descriptor comes out. I limited
      the amount of retries to 100 retries in order to avoid an infinite number
      of retries and so a busy-loop. Back then testing revealed that the
      number of retries were around 20-30 so 100 seemed a good upper limit.
      This g_zero test reaches without a problem 98 retries and it jumps
      sometimes to 101 on am335x-evm and so the WARN_ON() triggers. Same test
      run on beaglebone black and the retries start at 122 and my max value so
      far was at 128.
      So lets rise the limit to 500.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      6f9d7056
    • J
      dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model · 1e2dbdef
      Jingchang Lu 提交于
      The offset of all 8-/16-bit registers in big-endian eDMA model are
      swapped in a 32-bit size opposite those in the little-endian model.
      
      The hardware Scatter/Gather requires the subsequent TCDs stored in memory
      in little endian independent of the register endian model, the eDMA engine
      will do the swap if need.
      
      This patch also use regular assignment for tcd variables r/w
      instead of with io function previously that may not always be true.
      Signed-off-by: NJingchang Lu <jingchang.lu@freescale.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      1e2dbdef
  2. 08 12月, 2014 1 次提交
  3. 06 12月, 2014 4 次提交
  4. 05 12月, 2014 3 次提交
  5. 17 11月, 2014 22 次提交
  6. 06 11月, 2014 8 次提交