- 24 6月, 2016 1 次提交
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由 Kefeng Wang 提交于
Use helper of_platform_default_populate() in linux/of_platform when possible, instead of calling of_platform_populate() with the default match table. Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Krzysztof Halasa <khalasa@piap.pl> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Roland Stigge <stigge@antcom.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Ray Jui <rjui@broadcom.com> Cc: Viresh Kumar <vireshk@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: NRob Herring <robh@kernel.org>
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- 21 6月, 2016 1 次提交
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由 Andrey Smirnov 提交于
There's no need to explicitly call l2x0_of_init() since it will be called as a part of init_IRQ() (see arch/arm/kernel/irq.c for details). This way we can simplify imx_init_l2cache() and ditch the call to it on i.MX35 (which does not claim compatibility with "arm,pl310-cache") alltogether. Acked-by: NArnd Bergmann <arnd@arndb.de> Suggested-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 14 2月, 2016 1 次提交
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由 Bai Ping 提交于
The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version. Signed-off-by: NBai Ping <ping.bai@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 15 9月, 2015 2 次提交
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由 Viresh Kumar 提交于
That's the naming convention followed in most of opp core, but few routines didn't follow this, fix them. Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NShawn Guo <shawnguo@kernel.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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由 Viresh Kumar 提交于
free-table routines are opposite of init-table ones, and must be named to make that clear. Opposite of 'init' is 'exit', but those doesn't suit really well. Replace 'init' with 'add' and 'free' with 'remove'. Reported-by: NPavel Machek <pavel@ucw.cz> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NShawn Guo <shawnguo@kernel.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 03 6月, 2015 1 次提交
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由 Shawn Guo 提交于
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function") moves imx6_set_lpm() from clock init function into imx6_pm_common_init(). This causes a hang when cpuidle support is enabled. The reason for that is ARM core clock is shut down unexpectedly by WAIT mode. It happens with the following call stack: cpuidle_register_governor() cpuidle_switch_governor() cpuidle_uninstall_idle_handler() synchronize_sched() wait_rcu_gp() wait_for_completion() When wait_for_completion() is called as above, all cores are idle/WFI. Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a hardware shutdown of the ARM core clock. To fix the regression, we need to ensure that CCM_CLPCR_LPM is initialized into RUN mode earlier than cpuidle governor registration, which is a postcore_initcall. This patch creates function imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into RUN mode, and have the function called from machine .init_irq hook, which should be early enough. Reported-by: NKevin Hilman <khilman@kernel.org> Fixes: 8fb76a07 ("ARM: imx6: set initial power mode in pm function") Tested-by: NKevin Hilman <khilman@linaro.org> Tested-by: NTyler Baker <tyler.baker@linaro.org> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 30 3月, 2015 2 次提交
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由 Marc Zyngier 提交于
Now that the GPC has been converted to be a full blown irqchip (and not a mole on the side of the GIC), booting a new kernel with an old DT is likely to result in a rough ride for the user. This patch makes sure such a situation is promptly detected and the user made aware that a DT update is in order. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NJason Cooper <jason@lakedaemon.net> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Marc Zyngier 提交于
IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: NStefan Agner <stefan@agner.ch> Acked-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 12 3月, 2015 1 次提交
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由 Shawn Guo 提交于
Since commit 035a61c3 ("clk: Make clk API return per-user struct clk instances"), clk API users can no longer check if two struct clk pointers are pointing to the same hardware clock, i.e. struct clk_hw, by simply comparing two pointers. That's because with the per-user clk change, a brand new struct clk is created whenever clients try to look up the clock by calling clk_get() or sister functions like clk_get_sys() and of_clk_get(). This changes the original behavior where the struct clk is only created for once when clock driver registers the clock to CCF in the first place. The net change here is before commit 035a61c3 the struct clk pointer is unique for given hardware clock, while after the commit the pointers returned by clk lookup calls become different for the same hardware clock. That said, the struct clk pointer comparing in the code doesn't work any more. Call helper function clk_is_match() instead to fix the problem. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 20 1月, 2015 1 次提交
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imx6q_opp_check_speed_grading() remaps memory to the base variable and never unmaps it. I can't see how this can be of any use later so here I unmap it. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 09 1月, 2015 1 次提交
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由 Fabio Estevam 提交于
i.MX platform maintainer Shawn Guo is not happy with the such commit as explained below [1]: "The GPR difference between SoCs can be encoded in device tree as well. It's pointless to repeat the same code pattern for every single platform, that need to set up GPR bits for enabling magic packet wake up, while the only difference is the register and bit offset. The platform code will become quite messy and unmaintainable if every device driver dump their GPR register setup code into platform. Sorry, but it's NACK from me." This reverts commit 456062b3 ("ARM: imx: add FEC sleep mode callback function"). [1] http://www.spinics.net/lists/netdev/msg310922.htmlSigned-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 01 1月, 2015 1 次提交
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由 Nimrod Andy 提交于
i.MX6q/dl, i.MX6SX SOCs enet support sleep mode that magic packet can wake up system in suspend status. For different SOCs, there have some SOC specifical GPR register to set sleep on/off mode. So add these to callback function for driver. Signed-off-by: NFugang Duan <B38611@freescale.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 11月, 2014 1 次提交
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由 Jingchang Lu 提交于
System restart mechanism has been changed with the introduction of "kernel restart handler call chain support". The imx2 watchdog based restart handler has been moved to the driver, and these restart can be removed from the machine layer. This patch cleans up the device tree version machine reset init with mxc_arch_reset_init_dt and removes corresponding .restart handler, for the .init_machine that can be handled by system default after removing the mxc_arch_reset_init_dt, the .init_machine is also removed. Signed-off-by: NJingchang Lu <jingchang.lu@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 18 7月, 2014 2 次提交
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由 Shawn Guo 提交于
Otherwise GCC will mark the .init.rodata section R/W, which causes a compile error once we add other real R/O data. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Fabio Estevam 提交于
It is only the mx6quad variant that can run up to 1.2GHz, so add the check accordingly. This avoids getting the following warning on a mx6solo: failed to disable 1.2 GHz OPP Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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- 05 3月, 2014 4 次提交
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由 Philipp Zabel 提交于
This is needed so that the IPU framebuffer scanout cannot be starved by VPU or GPU activity. Some boards like the SabreLite and SabreSD seem to set this in the DCD already, but the documented register reset values do not contain the necessary settings. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Anson Huang 提交于
The fuse map of speed_grading[1:0] defines the max speed of ARM, see below the definition: 2b'11: 1200000000Hz; 2b'10: 996000000Hz; 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 2b'00: 792000000Hz; Need to remove all illegal setpoints according to fuse map. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
On imx6qdl, the ENET RMII and PTP clock can come from either internal ANATOP/CCM or external clock source through pad GPIO_16. But in case of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared. The patch adds the support for systems that use an external clock source and distinguishes above two cases by checking if the PTP clock specified in device tree is the one coming from the internal ANATOP/CCM. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Anson Huang 提交于
When system enter suspend, we can set the DDR IO to high-Z state to save DDR IOs' power consumption, this operation can save many power(from ~26mA@1.5V to ~15mA@1.5V, measured on i.MX6Q SabreSD board, R25) of DDR IOs. To achieve that, we need to copy the suspend code to ocram and run the low level hardware related code(set DDR IOs to high-Z state) in ocram. If there is no ocram space available, then system will still do suspend in external DDR, hence no DDR IOs will be set to high-Z. The OCRAM usage layout is as below, ocram suspend region(4K currently): ======================== high address ====================== . . . ^ ^ ^ imx6_suspend code PM_INFO structure(imx6_cpu_pm_info) ======================== low address ======================= Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 27 1月, 2014 1 次提交
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由 Russell King 提交于
Add support for the SolidRun HummingBoard. This commit adds support for the following interfaces on this board: - Consumer Ir receiver - S/PDIF output - Both USB interfaces - Gigabit Ethernet using AR8035 - UART port Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 31 12月, 2013 1 次提交
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由 Shawn Guo 提交于
0-DAY kernel build testing backend reports the following. scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch # many are suggestions rather than must-fix ERROR: Use of const init definition must use __initconst #80: arch/arm/mach-imx/mach-imx50.c:26: +static const char *imx50_dt_board_compat[] __initdata = { While at it, fix the error globally for IMX platform. Reported-by: NFengguang Wu <fengguang.wu@intel.com> Acked-by: NGreg Ungerer <gerg@uclinux.org> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 09 12月, 2013 1 次提交
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由 Tim Harvey 提交于
The PEX860X has GPIO's which are used for PCI Reset lines on the Gateworks Ventana boards. The GPIO's need to be set as output level high so as to allow the PCIe devices to come out of reset. Signed-off-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 26 10月, 2013 2 次提交
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由 Nishanth Menon 提交于
Since Operating Performance Points (OPP) functions are specific to device specific power management, be specific and rename opp.h to pm_opp.h Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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由 Nishanth Menon 提交于
Since Operating Performance Points (OPP) functions are specific to device specific power management, be specific and rename opp_* accessors in OPP library with dev_pm_opp_* equivalent. Affected functions are: opp_get_voltage opp_get_freq opp_get_opp_count opp_find_freq_exact opp_find_freq_floor opp_find_freq_ceil opp_add opp_enable opp_disable opp_get_notifier opp_init_cpufreq_table opp_free_cpufreq_table Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 21 10月, 2013 4 次提交
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由 Shawn Guo 提交于
The imx6q_restart() works fine with normal reboot but will run into problem with emergency reboot like sysrq-b. In that case, of_iomap() gets called from interrupt context and hence triggers the BUG_ON in __get_vm_area_node(). Actually, since commit c1e31d12 (ARM: imx: create mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where things like of_iomap() can be done. The patch updates mxc_restart() a little bit to get it work for imx6q/dl and kill imx6q_restart() completely. Reported-by: NNathan Lynch <nathan_lynch@mentor.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
The patch enables soc bus infrastructure and adds a function imx_soc_device_init() to report soc info via soc device interface for imx6qdl and imx6sl. With the support, user space can get soc related info by looking at sysfs like below. $ cat /sys/devices/soc0/machine Freescale i.MX6 Quad SABRE Smart Device Board $ cat /sys/devices/soc0/family Freescale i.MX $ cat /sys/devices/soc0/soc_id i.MX6Q $ cat /sys/devices/soc0/revision 1.2 Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
It calls imx_set_soc_revision() to set up soc revision in imx6q_init_revision(), and replaces all the occurrences of imx6q_revision() with common helper imx_get_soc_revision(). Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 30 9月, 2013 1 次提交
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由 Sebastian Hesselbarth 提交于
With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NShawn Guo <shawn.guo@linaro.org>
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- 19 9月, 2013 1 次提交
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由 Sudeep KarkadaNagesha 提交于
Commit cdc58d60 "cpufreq: imx6q-cpufreq: remove device tree parsing for cpu nodes" assumed the pdev->dev is set to cpu0 device in the platform code. But it actually points to the virtual cpufreq-cpu0 platform device which is not present in the device tree. Most of the information needed by cpufreq is stored in cpu0 DT node. So cpu_dev must point to cpu0 device. This patch fixes the wrong assignment to cpu_dev. Reported-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NSudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 22 8月, 2013 3 次提交
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由 Shawn Guo 提交于
The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Dinh Nguyen 提交于
Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines. Also add support for the KSZ9021RLRN PHY. Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NDavid S. Miller <davem@davemloft.net> CC: Andrew Victor <linux@maxim.org.za> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Peter Chen 提交于
Move anatop related (For USB) from board file to anatop driver Signed-off-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 21 8月, 2013 1 次提交
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由 Sudeep KarkadaNagesha 提交于
Now that the cpu device registration initialises the of_node(if available) appropriately for all the cpus, parsing here is redundant. This patch removes all DT parsing and uses cpu->of_node instead. Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NSudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
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- 16 8月, 2013 5 次提交
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由 Shawn Guo 提交于
Move imx6q L2 initialization function imx6q_init_l2cache() into system.c, and rename it imx_init_l2cache(), so that other platforms other than imx6q can also use the function. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NDirk Behme <dirk.behme@de.bosch.com>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The KSZ9031 is used on the i.MX6 based Data Modul eDM-QMX6 board. It needs the same fixup to the rx/tx delays as other i.MX6 boards. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
The AR8031 is used on the i.MX6 based sabreSD, sabreauto and wandboard. All need the same fixup, so add it for all i.MX6. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
In current U-Boot the sabrelite, nitrogen6x and titanium all need the same fixup for the ksz9021 phy. Instead of limiting the fixup to a single board apply them for all. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 10 7月, 2013 1 次提交
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由 Robin Holt 提交于
Preparing to move the parsing of reboot= to generic kernel code forces the change in reboot_mode handling to use the enum. [akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c] Signed-off-by: NRobin Holt <holt@sgi.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Russ Anderson <rja@sgi.com> Cc: Robin Holt <holt@sgi.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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