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  1. 14 10月, 2011 1 次提交
  3. 27 7月, 2011 1 次提交
  5. 22 7月, 2011 1 次提交
    • F
      powerpc/85xx: fix mpic configuration in CAMP mode · a63e23b9
      由 Fabio Baltieri 提交于 
      Change the string to check for CAMP mode boot on MPC85xx (eg. P2020) to match
the one in the corresponding dts files (p2020rdb_camp_core{0,1}.dts).

Without this fix the mpic is configured as in the SMP boot mode, which causes
the first core to report a protected source interrupt error for devices
of the other core and lock up.

Also add MPIC_SINGLE_DEST_CPU on both P2020 based architectures in CAMP
mode as suggested by Scott Wood. Thanks.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NFabio Baltieri <fabio.baltieri@gmail.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      a63e23b9
  7. 08 7月, 2011 2 次提交
    • L
      powerpc/85xx: Remove stale BUG_ON in mpc85xx_smp_init · 2647aa19
      由 Laurentiu TUDOR 提交于 
      Under the FSL Hypervisor we triggered a BUG_ON in mpc85xx_smp_init that
expected smp_ops.message_pass to be explicity set.  However recent
changes allows smp_ops.message_pass to be NULL and handled by default
code.  Thus the BUG_ON isn't relevant anymore.
Signed-off-by: NLaurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      2647aa19
    • M
      powerpc/85xx: Add p2040 RDB board support · 3fce1c0b
      由 Mingkai Hu 提交于 
      P2040RDB Specification:
-----------------------
2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
128 Mbyte NOR flash single-chip memory
256 Kbit M24256 I2C EEPROM
16 Mbyte SPI memory
SD connector to interface with the SD memory card
dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
I2C1: Real time clock, Temperature sensor
I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
UART: supports two UARTs up to 115200 bps for console
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
PCIe:
 - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3fce1c0b
  9. 27 6月, 2011 6 次提交
  11. 23 6月, 2011 4 次提交
  13. 20 6月, 2011 1 次提交
  15. 10 6月, 2011 1 次提交
  17. 19 5月, 2011 1 次提交
    • M
      powerpc: Consolidate ipi message mux and demux · 23d72bfd
      由 Milton Miller 提交于 
      Consolidate the mux and demux of ipi messages into smp.c and call
a new smp_ops callback to actually trigger the ipi.

The powerpc architecture code is optimised for having 4 distinct
ipi triggers, which are mapped to 4 distinct messages (ipi many, ipi
single, scheduler ipi, and enter debugger).  However, several interrupt
controllers only provide a single software triggered interrupt that
can be delivered to each cpu.  To resolve this limitation, each smp_ops
implementation created a per-cpu variable that is manipulated with atomic
bitops.  Since these lines will be contended they are optimialy marked as
shared_aligned and take a full cache line for each cpu.  Distro kernels
may have 2 or 3 of these in their config, each taking per-cpu space
even though at most one will be in use.

This consolidation removes smp_message_recv and replaces the single call
actions cases with direct calls from the common message recognition loop.
The complicated debugger ipi case with its muxed crash handling code is
moved to debug_ipi_action which is now called from the demux code (instead
of the multi-message action calling smp_message_recv).

I put a call to reschedule_action to increase the likelyhood of correctly
merging the anticipated scheduler_ipi() hook coming from the scheduler
tree; that single required call can be inlined later.

The actual message decode is a copy of the old pseries xics code with its
memory barriers and cache line spacing, augmented with a per-cpu unsigned
long based on the book-e doorbell code.  The optional data is set via a
callback from the implementation and is passed to the new cause-ipi hook
along with the logical cpu number.  While currently only the doorbell
implemntation uses this data it should be almost zero cost to retrieve and
pass it -- it adds a single register load for the argument from the same
cache line to which we just completed a store and the register is dead
on return from the call.  I extended the data element from unsigned int
to unsigned long in case some other code wanted to associate a pointer.

The doorbell check_self is replaced by a call to smp_muxed_ipi_resend,
conditioned on the CPU_DBELL feature.  The ifdef guard could be relaxed
to CONFIG_SMP but I left it with BOOKE for now.

Also, the doorbell interrupt vector for book-e was not calling irq_enter
and irq_exit, which throws off cpu accounting and causes code to not
realize it is running in interrupt context.  Add the missing calls.
Signed-off-by: NMilton Miller <miltonm@bga.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      23d72bfd
  19. 04 5月, 2011 1 次提交
  21. 20 4月, 2011 1 次提交
  23. 29 3月, 2011 2 次提交
  25. 15 3月, 2011 1 次提交
    • K
      powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e · decbb280
      由 Kumar Gala 提交于 
      If the spin table is located in the linear mapping (which can happen if
we have 4G or more of memory) we need to access the spin table via a
cacheable coherent mapping like we do on ppc32 (and do explicit cache
flush).

See the following commit for the ppc32 version of this issue:

commit d1d47ec6
Author: Peter Tyser <ptyser@xes-inc.com>
Date:   Fri Dec 18 16:50:37 2009 -0600

    powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      decbb280
  27. 10 3月, 2011 1 次提交
  29. 03 1月, 2011 1 次提交
  31. 02 1月, 2011 1 次提交
  33. 15 10月, 2010 1 次提交
  35. 14 10月, 2010 7 次提交
  37. 08 10月, 2010 1 次提交
  39. 01 9月, 2010 2 次提交
  41. 05 8月, 2010 3 次提交