1. 04 4月, 2019 2 次提交
  2. 28 3月, 2019 5 次提交
  3. 24 3月, 2019 1 次提交
  4. 23 3月, 2019 5 次提交
  5. 22 3月, 2019 7 次提交
  6. 21 3月, 2019 15 次提交
    • Y
      irqchip/irq-mvebu-sei: Make mvebu_sei_ap806_caps static · f27b744b
      YueHaibing 提交于
      Fix sparse warning:
      
      drivers/irqchip/irq-mvebu-sei.c:481:23: warning:
       symbol 'mvebu_sei_ap806_caps' was not declared. Should it be static?
      Signed-off-by: NYueHaibing <yuehaibing@huawei.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: <jason@lakedaemon.net>
      Cc: <andrew@lunn.ch>
      Cc: <gregory.clement@bootlin.com>
      Cc: <sebastian.hesselbarth@gmail.com>
      Cc: <marc.zyngier@arm.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Link: https://lkml.kernel.org/r/20190321151448.15600-1-yuehaibing@huawei.com
      f27b744b
    • J
      irqchip/mbigen: Don't clear eventid when freeing an MSI · fca269f2
      Jianguo Chen 提交于
      mbigen_write_msg clears eventid bits of a mbigen register
      when free a interrupt, because msi_domain_deactivate memset
      struct msg to zero. Then multiple mbigen pins with zero eventid
      will report the same interrupt number.
      
      The eventid clear call trace:
                      free_irq
                      __free_irq
                      irq_shutdown
                      irq_domain_deactivate_irq
                      __irq_domain_deactivate_irq
                      __irq_domain_deactivate_irq
                      msi_domain_deactivate
                      platform_msi_write_msg
                      mbigen_write_msg
      Signed-off-by: NJianguo Chen <chenjianguo3@huawei.com>
      [maz: massaged subject]
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      fca269f2
    • F
      irqchip/stm32: Don't set rising configuration registers at init · 6a77623d
      Fabien Dessenne 提交于
      The rising configuration status register (rtsr) is not banked.
      As it is shared with the co-processor, it should not be written at probe
      time, else the co-processor configuration will be lost.
      
      Fixes: f9fc1745 ("irqchip/stm32: Add host and driver data structures")
      Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      6a77623d
    • F
      irqchip/stm32: Don't clear rising/falling config registers at init · 0dda0966
      Fabien Dessenne 提交于
      Falling and rising configuration and status registers are not banked.
      As they are shared with M4 co-processor, they should not be cleared
      at probe time, else M4 co-processor configuration will be lost.
      
      Fixes: f9fc1745 ("irqchip/stm32: Add host and driver data structures")
      Signed-off-by: NLoic Pallardy <loic.pallardy@st.com>
      Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      0dda0966
    • Y
      irqchip/mmp: Make mmp_irq_domain_ops static · 096048cb
      YueHaibing 提交于
      Fix sparse warning:
      
      drivers/irqchip/irq-mmp.c:182:29: warning:
       symbol 'mmp_irq_domain_ops' was not declared. Should it be static?
      Signed-off-by: NYueHaibing <yuehaibing@huawei.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      096048cb
    • Y
      irqchip/brcmstb-l2: Make two init functions static · dc3173c7
      YueHaibing 提交于
      Fix sparse warnings:
      
      drivers/irqchip/irq-brcmstb-l2.c:278:12: warning:
       symbol 'brcmstb_l2_edge_intc_of_init' was not declared. Should it be static?
      drivers/irqchip/irq-brcmstb-l2.c:285:12: warning:
       symbol 'brcmstb_l2_lvl_intc_of_init' was not declared. Should it be static?
      Signed-off-by: NYueHaibing <yuehaibing@huawei.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      dc3173c7
    • W
      mmc: renesas_sdhi: limit block count to 16 bit for old revisions · c9a9497c
      Wolfram Sang 提交于
      R-Car Gen2 has two different SDHI incarnations in the same chip. The
      older one does not support the recently introduced 32 bit register
      access to the block count register. Make sure we use this feature only
      after the first known version.
      
      Thanks to the Renesas Testing team for this bug report!
      
      Fixes: 5603731a ("mmc: tmio: fix access width of Block Count Register")
      Reported-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
      Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
      Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
      Tested-by: NPhong Hoang <phong.hoang.wz@renesas.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      c9a9497c
    • D
      mmc: alcor: fix DMA reads · 5ea47691
      Daniel Drake 提交于
      Setting max_blk_count to 1 here was causing the mmc block layer
      to always use the MMC_READ_SINGLE_BLOCK command here, which the
      driver does not DMA-accelerate.
      
      Drop the max_blk_ settings here. The mmc host defaults suffice,
      along with the max_segs and max_seg_size settings, which I have
      now documented in more detail.
      
      Now each MMC command reads 4 512-byte blocks, using DMA instead of
      PIO. On my SD card, this increases read performance (measured with dd)
      from 167kb/sec to 4.6mb/sec.
      
      Link: http://lkml.kernel.org/r/CAD8Lp47L5T3jnAjBiPs1cQ+yFA3L6LJtgFvMETnBrY63-Zdi2g@mail.gmail.comSigned-off-by: NDaniel Drake <drake@endlessm.com>
      Reviewed-by: NOleksij Rempel <linux@rempel-privat.de>
      Fixes: c5413ad8 ("mmc: add new Alcor Micro Cardreader SD/MMC driver")
      Cc: stable@vger.kernel.org
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      5ea47691
    • K
      mmc: sdhci-omap: Set caps2 to indicate no physical write protect pin · 031d2ccc
      Kishon Vijay Abraham I 提交于
      After commit 6d5cd068 ("mmc: sdhci: use WP GPIO in
      sdhci_check_ro()") and commit 39ee32ce ("mmc: sdhci-omap: drop
      ->get_ro() implementation"), sdhci-omap relied on SDHCI_PRESENT_STATE
      to check if the card is read-only, if wp-gpios is not populated
      in device tree. However SDHCI_PRESENT_STATE in sdhci-omap does not have
      correct read-only state.
      
      sdhci-omap can be used by platforms with both micro SD slot and standard
      SD slot with physical write protect pin (using GPIO). Set caps2 to
      MMC_CAP2_NO_WRITE_PROTECT based on if wp-gpios property is populated or
      not.
      
      This fix is required since existing device-tree node doesn't have
      "disable-wp" property and to preserve old-dt compatibility.
      
      Fixes: 6d5cd068 ("mmc: sdhci: use WP GPIO in sdhci_check_ro()")
      Fixes: 39ee32ce ("mmc: sdhci-omap: drop ->get_ro() implementation")
      Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      031d2ccc
    • A
      mmc: mxcmmc: "Revert mmc: mxcmmc: handle highmem pages" · 2b77158f
      Alexander Shiyan 提交于
      This reverts commit b189e758.
      
      Unable to handle kernel paging request at virtual address c8358000
      pgd = efa405c3
      [c8358000] *pgd=00000000
      Internal error: Oops: 805 [#1] PREEMPT ARM
      CPU: 0 PID: 711 Comm: kworker/0:2 Not tainted 4.20.0+ #30
      Hardware name: Freescale i.MX27 (Device Tree Support)
      Workqueue: events mxcmci_datawork
      PC is at mxcmci_datawork+0xbc/0x2ac
      LR is at mxcmci_datawork+0xac/0x2ac
      pc : [<c04e33c8>]    lr : [<c04e33b8>]    psr: 60000013
      sp : c6c93f08  ip : 24004180  fp : 00000008
      r10: c8358000  r9 : c78b3e24  r8 : c6c92000
      r7 : 00000000  r6 : c7bb8680  r5 : c7bb86d4  r4 : c78b3de0
      r3 : 00002502  r2 : c090b2e0  r1 : 00000880  r0 : 00000000
      Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
      Control: 0005317f  Table: a68a8000  DAC: 00000055
      Process kworker/0:2 (pid: 711, stack limit = 0x389543bc)
      Stack: (0xc6c93f08 to 0xc6c94000)
      3f00:                   c7bb86d4 00000000 00000000 c6cbfde0 c7bb86d4 c7ee4200
      3f20: 00000000 c0907ea8 00000000 c7bb86d8 c0907ea8 c012077c c6cbfde0 c7bb86d4
      3f40: c6cbfde0 c6c92000 c6cbfdf4 c09280ba c0907ea8 c090b2e0 c0907ebc c0120c18
      3f60: c6cbfde0 00000000 00000000 c6cbb580 c7ba7c40 c7837edc c6cbb598 00000000
      3f80: c6cbfde0 c01208f8 00000000 c01254fc c7ba7c40 c0125400 00000000 00000000
      3fa0: 00000000 00000000 00000000 c01010d0 00000000 00000000 00000000 00000000
      3fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      3fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
      [<c04e33c8>] (mxcmci_datawork) from [<c012077c>] (process_one_work+0x1f0/0x338)
      [<c012077c>] (process_one_work) from [<c0120c18>] (worker_thread+0x320/0x474)
      [<c0120c18>] (worker_thread) from [<c01254fc>] (kthread+0xfc/0x118)
      [<c01254fc>] (kthread) from [<c01010d0>] (ret_from_fork+0x14/0x24)
      Exception stack(0xc6c93fb0 to 0xc6c93ff8)
      3fa0:                                     00000000 00000000 00000000 00000000
      3fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      3fe0: 00000000 00000000 00000000 00000000 00000013 00000000
      Code: e3500000 1a000059 e5153050 e5933038 (e48a3004)
      ---[ end trace 54ca629b75f0e737 ]---
      note: kworker/0:2[711] exited with preempt_count 1
      Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
      Fixes: b189e758 ("mmc: mxcmmc: handle highmem pages")
      Cc: stable@vger.kernel.org
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      2b77158f
    • A
      drm/exynos/mixer: fix MIXER shadow registry synchronisation code · 6a3b45ad
      Andrzej Hajda 提交于
      MIXER on Exynos5 SoCs uses different synchronisation method than Exynos4
      to update internal state (shadow registers).
      Apparently the driver implements it incorrectly. The rule should be
      as follows:
      - do not request updating registers until previous request was finished,
        ie. MXR_CFG_LAYER_UPDATE_COUNT must be 0.
      - before setting registers synchronisation on VSYNC should be turned off,
        ie. MXR_STATUS_SYNC_ENABLE should be reset,
      - after finishing MXR_STATUS_SYNC_ENABLE should be set again.
      The patch hopefully implements it correctly.
      Below sample kernel log from page fault caused by the bug:
      
      [   25.670038] exynos-sysmmu 14650000.sysmmu: 14450000.mixer: PAGE FAULT occurred at 0x2247b800
      [   25.677888] ------------[ cut here ]------------
      [   25.682164] kernel BUG at ../drivers/iommu/exynos-iommu.c:450!
      [   25.687971] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
      [   25.693778] Modules linked in:
      [   25.696816] CPU: 5 PID: 1553 Comm: fb-release_test Not tainted 5.0.0-rc7-01157-g5f86b1566bdd #136
      [   25.705646] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
      [   25.711710] PC is at exynos_sysmmu_irq+0x1c0/0x264
      [   25.716470] LR is at lock_is_held_type+0x44/0x64
      
      v2: added missing MXR_CFG_LAYER_UPDATE bit setting in mixer_enable_sync
      Reported-by: NMarian Mihailescu <mihailescu2m@gmail.com>
      Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
      Signed-off-by: NInki Dae <inki.dae@samsung.com>
      6a3b45ad
    • T
      scsi: ibmvscsi: Fix empty event pool access during host removal · 7f5203c1
      Tyrel Datwyler 提交于
      The event pool used for queueing commands is destroyed fairly early in the
      ibmvscsi_remove() code path. Since, this happens prior to the call so
      scsi_remove_host() it is possible for further calls to queuecommand to be
      processed which manifest as a panic due to a NULL pointer dereference as
      seen here:
      
      PANIC: "Unable to handle kernel paging request for data at address
      0x00000000"
      
      Context process backtrace:
      
      DSISR: 0000000042000000 ????Syscall Result: 0000000000000000
      4 [c000000002cb3820] memcpy_power7 at c000000000064204
      [Link Register] [c000000002cb3820] ibmvscsi_send_srp_event at d000000003ed14a4
      5 [c000000002cb3920] ibmvscsi_send_srp_event at d000000003ed14a4 [ibmvscsi] ?(unreliable)
      6 [c000000002cb39c0] ibmvscsi_queuecommand at d000000003ed2388 [ibmvscsi]
      7 [c000000002cb3a70] scsi_dispatch_cmd at d00000000395c2d8 [scsi_mod]
      8 [c000000002cb3af0] scsi_request_fn at d00000000395ef88 [scsi_mod]
      9 [c000000002cb3be0] __blk_run_queue at c000000000429860
      10 [c000000002cb3c10] blk_delay_work at c00000000042a0ec
      11 [c000000002cb3c40] process_one_work at c0000000000dac30
      12 [c000000002cb3cd0] worker_thread at c0000000000db110
      13 [c000000002cb3d80] kthread at c0000000000e3378
      14 [c000000002cb3e30] ret_from_kernel_thread at c00000000000982c
      
      The kernel buffer log is overfilled with this log:
      
      [11261.952732] ibmvscsi: found no event struct in pool!
      
      This patch reorders the operations during host teardown. Start by calling
      the SRP transport and Scsi_Host remove functions to flush any outstanding
      work and set the host offline. LLDD teardown follows including destruction
      of the event pool, freeing the Command Response Queue (CRQ), and unmapping
      any persistent buffers. The event pool destruction is protected by the
      scsi_host lock, and the pool is purged prior of any requests for which we
      never received a response. Finally, move the removal of the scsi host from
      our global list to the end so that the host is easily locatable for
      debugging purposes during teardown.
      
      Cc: <stable@vger.kernel.org> # v2.6.12+
      Signed-off-by: NTyrel Datwyler <tyreld@linux.vnet.ibm.com>
      Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
      7f5203c1
    • T
      scsi: ibmvscsi: Protect ibmvscsi_head from concurrent modificaiton · 7205981e
      Tyrel Datwyler 提交于
      For each ibmvscsi host created during a probe or destroyed during a remove
      we either add or remove that host to/from the global ibmvscsi_head
      list. This runs the risk of concurrent modification.
      
      This patch adds a simple spinlock around the list modification calls to
      prevent concurrent updates as is done similarly in the ibmvfc driver and
      ipr driver.
      
      Fixes: 32d6e4b6 ("scsi: ibmvscsi: add vscsi hosts to global list_head")
      Cc: <stable@vger.kernel.org> # v4.10+
      Signed-off-by: NTyrel Datwyler <tyreld@linux.vnet.ibm.com>
      Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
      7205981e
    • L
      scsi: hisi_sas: Add softreset in hisi_sas_I_T_nexus_reset() · 0e83fc61
      Luo Jiaxing 提交于
      We found out that for v2 hw, a SATA disk can not be written to after the
      system comes up.
      
      In commit ffb1c820 ("scsi: hisi_sas: remove the check of sas_dev status
      in hisi_sas_I_T_nexus_reset()"), we introduced a path where we may issue an
      internal abort for a SATA device, but without following it with a
      softreset.
      
      We need to always follow an internal abort with a software reset, as per HW
      programming flow, so add this.
      
      Fixes: ffb1c820 ("scsi: hisi_sas: remove the check of sas_dev status in hisi_sas_I_T_nexus_reset()")
      Signed-off-by: NLuo Jiaxing <luojiaxing@huawei.com>
      Signed-off-by: NJohn Garry <john.garry@huawei.com>
      Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
      0e83fc61
    • R
      irqchip/gic-v3-its: Fix comparison logic in lpi_range_cmp · 89dc8917
      Rasmus Villemoes 提交于
      The lpi_range_list is supposed to be sorted in ascending order of
      ->base_id (at least if the range merging is to work), but the current
      comparison function returns a positive value if rb->base_id >
      ra->base_id, which means that list_sort() will put A after B in that
      case - and vice versa, of course.
      
      Fixes: 880cb3cd (irqchip/gic-v3-its: Refactor LPI allocator)
      Cc: stable@vger.kernel.org (v4.19+)
      Signed-off-by: NRasmus Villemoes <linux@rasmusvillemoes.dk>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      89dc8917
  7. 20 3月, 2019 5 次提交