Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org>
Tested-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

There are clock controller registers in the APCS block, which purpose
is to control the main CPU mux and divider. Add the clock properties as
part of the APCS device-tree node.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The APCS block was exposed until now as a syscon, but now we have a
proper driver for this block. Add the compatible string of the new
driver to probe and register the mailbox functionality.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add a device tree node for the A53 PLL, which exists on msm8916
platforms.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The QUP core can be used either for I2C or SPI, so the same IP is mapped
by a driver or the other. SPI bindings use a leading 0 for the start
address and a size of 0x600, I2C bindings don't have the leading 0 and
have a size 0x1000.

To make them more similar, add the leading 0 to I2C bindings and changes
the size to 0x500 for all of them, as this is the actual size of these
blocks. Also align the second entry of the clocks array.
Signed-off-by: NDamien Riegel <damien.riegel@savoirfairelinux.com>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

SMSM is not symmetrical, the incoming bits from WCNSS are available at
index 6, but the outgoing host id for WCNSS is 3. Further more, upstream
references the base of APCS (in contrast to downstream), so the register
offset of 8 must be included.

Fixes: 1fb47e0a ("arm64: dts: qcom: msm8916: Add smsm and smp2p nodes")
Cc: stable@vger.kernel.org
Reported-by: NRamon Fried <rfried@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add a missing #phy-cells to the dsi-phy, to silence dtc warning.

Cc: Archit Taneja <architt@codeaurora.org>
Fixes: 305410ff ("arm64: dts: msm8916: Add display support")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using
the following command:

perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*'
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Now that we have a binding defined for the shared file system memory use
this to describe the rmtfs memory region.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This shrinks the address size down to 89000 from its previous 90000
which was mistakenly pulled from downstream.
Signed-off-by: NCraig Tatlor <ctatlor97@gmail.com>
Acked-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

On msm8916 and msm8996 boards a secure io-write is used to write the
magic for selecting "download mode", specify this address in the
DeviceTree.

Note that qcom_scm.download_mode=1 must be specified on the kernel
command line for the kernel to attempt selecting download mode.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds the IOMMU node for the IOMMU that resides on the
Qualcomm MSM8916 platforms.
Signed-off-by: NRob Clark <robdclark@gmail.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds the Qualcomm Venus video codec node for the video
codec hardware residing on MSM8916 platforms.
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NRob Clark <robdclark@gmail.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds the Qualcomm Adreno GPU node that exists in the
MSM8916.
Signed-off-by: NRob Clark <robdclark@gmail.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Replace the obsolete compatible string for Coresight programmable
replicator with the new one.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add debug unit on Qualcomm msm8916 based platforms, including the
DragonBoard 410c board.
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

We currently have three device nodes for the same USB hardware
block, as evident by the reuse of the same reg address multiple
times. Now that the chipidea driver fully supports OTG with the
MSM wrapper we can collapse all these nodes into one USB device
node, reflecting the true nature of the hardware.
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

It's necessary to reference the xo clock and cx supply, so specify these
in the node. Also move the Hexagon smd-edge into the hexagon node, to
enable SSR.

As cxo is not yet available we reference the fixed version of cxo for
now, which will work until proper power management is implemented.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The PMU on msm8916 is for the cortex-a53 type CPU. Update the
compatible to the more specific one so we can get the a53
specific events out of the PMU.
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add initial set of CoreSight components found on Qualcomm msm8916 and
apq8016 based platforms, including the DragonBoard 410c board.
Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add the wcnss remoteproc node the SMD edge and the wcnss ctrl, bluetooth
and wifi nodes specified and enable this on db410c.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The rpmcc driver is providing the XO clock, which is the parent of almost
all clocks. But during boot, this driver may probe later and leave most of
the clocks without parent. The common clock framework currently reports
invalid rate for orphan clocks and this may confuse drivers.

To resolve this, use fixed clocks registration until we have some support
to deal with the this issue. Removing the generic rpmcc compatible is
enough to switch back to fixed factor XO clock.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add xo entry to sdhc clock node on all qcom platforms.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch add support to Analog audio both Playback and Capture via
msm8916 WCD muti codec.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The Hexagon core on the msm8916 provides services for audio control,
audio output, sensors and the Hexagon SDK. The Hexagon remoteproc node
allows us to boot this core.

Although its part of the core platform its left disabled as it will
crash without the rmtfs QMI service and we do not yet handle crashes
gracefully.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add the Hexagon SMD edge, so that QRTR is probed when the Hexagon is
booted.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The MSM8916 SoC contains a MDP5 based display block, and one DSI output.
Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children
sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's
input port.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add thermal zones, tsens and qfprom nodes
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

When a device uses the GIC as its interrupt controller and generates
SPIs, only the values 1 (edge rising) and 4 (level high) are legal.

Anything else is just plain wrong (can't be programmed into the HW),
and leads to aborted driver probes (USB doesn't work with 4.8-rc1
on a Dragonboard 410C).
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The TCSR memory segment includes various functionality, among other
things the halt-registers for the Hexagon.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

On msm8916 SCM acts as a controller for the MSS_RESET found in the GCC,
update the DT node so that we can address this.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The modem boot authenticator needs space to play in, this is supposed to
be relocatable and as such could later be replaced with a dynamically
allocated chunk of memory. But let's give it a reserve for now, as we
know that works.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds the smsm and smp2p nodes for the hexagon and wcnss
cores.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This adds the devicetree node for the SCM firmware.
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>

Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add device bindings for CPUs to suspend using PSCI as the enable-method.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NLina Iyer <lina.iyer@linaro.org>
Tested-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds lpass node to the SOC.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>