Since this phy is shared by multiple devices including USB and PCIe,
it is necessary to determine which device use this phy.
This patch adds SoC-dependent functions to determine a device using
this phy.

When there is 'socionext,syscon' property in the pcie-phy node,
the driver calls SoC-dependt function instead of checking .has_syscon
in SoC-dependent data. The function configures the system controller
to use phy for PCIe.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add legacy SoC support that needs to manage gio clock and reset and to skip
setting unimplemented phy parameters. This supports Pro5.

This specifies only 1 port use because Pro5 doesn't set it in the power-on
sequence.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In case of using default parameters, communication failure might occur
in rare cases. This sets Rx sync mode parameter to avoid the issue.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add legacy SoC support that needs to manage gio clock and reset.
This supports Pro5.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is
equivalent to Pro4.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use devm_platform_ioremap_resource() to simplify the code.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.

Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Implement single link subnode support to the phy driver.
Add reset support including PHY reset and individual lane reset.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add platform dependent initialization data for Torrent PHY used in TI's
J721E SoC.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use regmap to read and write DPTX specific PHY registers.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use regmap for accessing Torrent PHY registers. Modify register offsets
as defined in Torrent PHY user guide. Abstract address calculation
using regmap APIs.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add support for PHY configuration APIs. These will mainly reconfigure
link rate, number of lanes, voltage swing and pre-emphasis values.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add configuration functions for 19.2 MHz refclock support.
Add register configurations for SSC support.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a separate function to set different power state values.
Use uniform polling timeout value. Also check return values
of functions for proper error handling.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a wrapper function to write Torrent PHY registers to improve
code readability.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

- Change private data struct cdns_dp_phy to cdns_torrent_phy
- Change module description and registration accordingly
- Generic torrent functions have prefix cdns_torrent_phy_*
- Functions specific to Torrent phy for DisplayPort are prefixed as
  cdns_torrent_dp_*
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
to make it more generic for future use. Modifiy Makefile and Kconfig
accordingly. Also, change driver compatible from "cdns,dp-phy" to
"cdns,torrent-phy".This will not affect ABI as the driver has never
been functional, and therefore do not exist in any active use case.
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add the GEN3 QHP PCIe PHY found in SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for the GEN2 PCIe QMP PHY found in SDM845.
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p).
Hence, IS_ERR(p) is unneeded.

The semantic patch that generates this commit is as follows:

// <smpl>
@@
expression ptr;
constant error_code;
@@
-IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code)
+PTR_ERR(ptr) == - error_code
// </smpl>

Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.orgSigned-off-by: NMasahiro Yamada <masahiroy@kernel.org>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Acked-by: Stephen Boyd <sboyd@kernel.org> [drivers/clk/clk.c]
Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [GPIO]
Acked-by: Wolfram Sang <wsa@the-dreams.de> [drivers/i2c]
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [acpi/scan.c]
Acked-by: NRob Herring <robh@kernel.org>
Cc: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

If CONFIG_OF_ADDRESS is not set and COMPILE_TEST=y, the following
error is seen while building phy-j721e-wiz.c

drivers/phy/ti/phy-j721e-wiz.o: In function `wiz_remove':
phy-j721e-wiz.c:(.text+0x1a): undefined reference to
`of_platform_device_destroy'

Fix the config dependency for PHY_J721E_WIZ here.
Reported-by: NHulk Robot <hulkci@huawei.com>
Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: NHongbo Yao <yaohongbo@huawei.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20200117212310.2864-1-kishon@ti.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

In case of error, the function devm_ioremap() returns NULL pointer not
ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

commit 95f1061f715e ("phy: intel-lgm-emmc: Add support for eMMC PHY")
introduces the below warning

   WARNING: modpost: missing MODULE_LICENSE() in
   drivers/phy/intel/phy-intel-emmc.o

Fix it by adding missing MODULE_LICENSE.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Reviewed-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Some platforms e.g. J721e need lane swap register
to be programmed before reset is deasserted.
This patch ensures that we propagate the phy_reset
back to the reset controller driver.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Reviewed-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The pointer regmap is being initialized with a value that is never
read and it is being updated later with a new value from
phy->regmap_common_cdb.  The initialization is redundant and can be
removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Some of the phy drivers can be compile tested to increase build
coverage.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Adjust indentation from spaces to tab (+optional two spaces) as in
coding style.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NStanley Chu <stanley.chu@mediatek.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add support for eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: NRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Reviewed-by: NAndy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig), two divider clocks and supports
resets for each of the lanes.

[jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper]
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY"),
incorrectly used parent device pointer to get driver data. Fix it here.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Sierra SERDES IP supports upto 16 lanes (though not all of it
will be enabled in a platform). Allow Sierra driver to support a
maximum of upto 16 lanes.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Check for PLL lock during PHY power on.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

A link may have multiple lanes each with a separate reset. Get
reset control "array" in order to reset all the lanes associated
with the link.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The existing configuration done in Cadence Sierra driver is only for
reference and is not used in any platforms. Remove them and configure
both lane cdb and common cdb registers to be used with external
SSC configuration. This is validated in TI J721E platform.
Signed-off-by: NAnil Varughese <aniljoy@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

No functional change. Modify register offset macro names to be in sync with
Sierra user guide.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Instead of invoking cdns_sierra_phy_init() from probe, add it in
phy_ops so that it's initialized when the PHY consumer invokes
phy_init()
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add
support to use Cadence Sierra driver in J721E SoC.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>