Since this phy is shared by multiple devices including USB and PCIe,
it is necessary to determine which device use this phy.
This patch adds SoC-dependent functions to determine a device using
this phy.

When there is 'socionext,syscon' property in the pcie-phy node,
the driver calls SoC-dependt function instead of checking .has_syscon
in SoC-dependent data. The function configures the system controller
to use phy for PCIe.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add legacy SoC support that needs to manage gio clock and reset and to skip
setting unimplemented phy parameters. This supports Pro5.

This specifies only 1 port use because Pro5 doesn't set it in the power-on
sequence.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In case of using default parameters, communication failure might occur
in rare cases. This sets Rx sync mode parameter to avoid the issue.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add legacy SoC support that needs to manage gio clock and reset.
This supports Pro5.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is
equivalent to Pro4.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use devm_platform_ioremap_resource() to simplify the code.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.

Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Implement single link subnode support to the phy driver.
Add reset support including PHY reset and individual lane reset.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add platform dependent initialization data for Torrent PHY used in TI's
J721E SoC.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use regmap to read and write DPTX specific PHY registers.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Use regmap for accessing Torrent PHY registers. Modify register offsets
as defined in Torrent PHY user guide. Abstract address calculation
using regmap APIs.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add support for PHY configuration APIs. These will mainly reconfigure
link rate, number of lanes, voltage swing and pre-emphasis values.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add configuration functions for 19.2 MHz refclock support.
Add register configurations for SSC support.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a separate function to set different power state values.
Use uniform polling timeout value. Also check return values
of functions for proper error handling.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a wrapper function to write Torrent PHY registers to improve
code readability.
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

- Change private data struct cdns_dp_phy to cdns_torrent_phy
- Change module description and registration accordingly
- Generic torrent functions have prefix cdns_torrent_phy_*
- Functions specific to Torrent phy for DisplayPort are prefixed as
  cdns_torrent_dp_*
Signed-off-by: NSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
to make it more generic for future use. Modifiy Makefile and Kconfig
accordingly. Also, change driver compatible from "cdns,dp-phy" to
"cdns,torrent-phy".This will not affect ABI as the driver has never
been functional, and therefore do not exist in any active use case.
Signed-off-by: NYuti Amonkar <yamonkar@cadence.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add the GEN3 QHP PCIe PHY found in SDM845.
Tested-by: NJulien Massot <jmassot@softbankrobotics.com>
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for the GEN2 PCIe QMP PHY found in SDM845.
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In order to allow the GICv4 code to link properly on 32bit ARM,
make sure we don't use 64bit divisions when it isn't strictly
necessary.

Fixes: 4e6437f1 ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level")
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This is a merge error on my part - the driver was merged into mainline
by commit c5951e7c ("Merge tag 'mips_5.6' of git://../mips/linux")
over a week ago, but nobody apparently noticed that it didn't actually
build due to still having a reference to the devm_ioremap_nocache()
function, removed a few days earlier through commit 6a1000bd ("Merge
tag 'ioremap-5.6' of git://../ioremap").

Apparently this didn't get any build testing anywhere.  Not perhaps all
that surprising: it's restricted to 64-bit MIPS only, and only with the
new SGI_MFD_IOC3 support enabled.

I only noticed because the ioremap conflicts in the ARM SoC driver
update made me check there weren't any others hiding, and I found this
one.
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The configuration of the OCTEONTX XCV_DLL_CTL register via
xcv_init_hw() is such that the RGMII RX delay is bypassed
leaving the RGMII TX delay enabled in the MAC:

	/* Configure DLL - enable or bypass
	 * TX no bypass, RX bypass
	 */
	cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL);
	cfg &= ~0xFF03;
	cfg |= CLKRX_BYP;
	writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);

This would coorespond to a interface type of PHY_INTERFACE_MODE_RGMII_RXID
and not PHY_INTERFACE_MODE_RGMII.

Fixing this allows RGMII PHY drivers to do the right thing (enable
RX delay in the PHY) instead of erroneously enabling both delays in the
PHY.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

V{PEND,PROP}BASER registers are actually located in VLPI_base frame
of the *redistributor*. Rename their accessors to reflect this fact.

No functional changes.
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-7-yuzenghui@huawei.com

"ITS virtual pending table not cleaning" is already complained inside
its_clear_vpend_valid(), there's no need to trigger a WARN_ON again.
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-6-yuzenghui@huawei.com

The variable 'tmp' in inherit_vpe_l1_table_from_rd() is actually
not needed, drop it.
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-5-yuzenghui@huawei.com

In GICv4, we will ensure that level2 vPE table memory is allocated
for the specified vpe_id on all v4 ITS, in its_alloc_vpe_table().
This still works well for the typical GICv4.1 implementation, where
the new vPE table is shared between the ITSs and the RDs.

To make it explicit, let us introduce allocate_vpe_l2_table() to
make sure that the L2 tables are allocated on all v4.1 RDs. We're
likely not need to allocate memory in it because the vPE table is
shared and (L2 table is) already allocated at ITS level, except
for the case where the ITS doesn't share anything (say SVPET == 0,
practically unlikely but architecturally allowed).

The implementation of allocate_vpe_l2_table() is mostly copied from
its_alloc_table_entry().
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-4-yuzenghui@huawei.com

Currently, we will not set vpe_l1_page for the current RD if we can
inherit the vPE configuration table from another RD (or ITS), which
results in an inconsistency between RDs within the same CommonLPIAff
group.

Let's rename it to vpe_l1_base to indicate the base address of the
vPE configuration table of this RD, and set it properly for *all*
v4.1 redistributors.
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-3-yuzenghui@huawei.com

The Size field of GICv4.1 VPROPBASER register indicates number of
pages minus one and together Page_Size and Size control the vPEID
width. Let's respect this requirement of the architecture.
Signed-off-by: NZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: NMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-2-yuzenghui@huawei.com

Fix u8 cast reading max_nss from MT_TOP_STRAP_STA register in
mt7615_eeprom_parse_hw_cap routine

Fixes: acf5457f ("mt76: mt7615: read {tx,rx} mask from eeprom")
Signed-off-by: NLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

The former contains nothing but a pointer to an array of the latter...
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

Unused now.
Signed-off-by: NEric Sandeen <sandeen@redhat.com>
Acked-by: NDavid Howells <dhowells@redhat.com>
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

fs_parse() analogue taking p_log instead of fs_context.
fs_parse() turned into a wrapper, callers in ceph_common and rbd
switched to __fs_parse().

As the result, fs_parse() never gets NULL fs_context and neither
do fs_context-based logging primitives
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

primitives for prefixed logging
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

In case devlink_dpipe_entry_ctx_prepare() failed, release RTNL that was
previously taken and free the memory allocated by
mlxsw_sp_erif_entry_prepare().

Fixes: 2ba5999f ("mlxsw: spectrum: Add Support for erif table entries access")
Signed-off-by: NIdo Schimmel <idosch@mellanox.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When reading the number of gearboxes from the hardware, the driver does
not validate the returned 'device type' field. The driver can therefore
wrongly assume that the queried devices are gearboxes.

On Spectrum-3 systems that support different types of devices, this can
prevent the driver from loading, as it will try to query the
temperature sensors from devices which it assumes are gearboxes and in
fact are not.

For example:
[  218.129230] mlxsw_minimal 2-0048: Reg cmd access status failed (status=7(bad parameter))
[  218.138282] mlxsw_minimal 2-0048: Reg cmd access failed (reg_id=900a(mtmp),type=write)
[  218.147131] mlxsw_minimal 2-0048: Failed to setup temp sensor number 256
[  218.534480] mlxsw_minimal 2-0048: Fail to register core bus
[  218.540714] mlxsw_minimal: probe of 2-0048 failed with error -5

Fix this by validating the 'device type' field.

Fixes: 2e265a8b ("mlxsw: core: Extend hwmon interface with inter-connect temperature attributes")
Fixes: f14f4e62 ("mlxsw: core: Extend thermal core with per inter-connect device thermal zones")
Signed-off-by: NVadim Pasternak <vadimp@mellanox.com>
Acked-by: NJiri Pirko <jiri@mellanox.com>
Signed-off-by: NIdo Schimmel <idosch@mellanox.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Unlike IPv4, in IPv6 there is no unique structure to represent the
nexthop and both the route and nexthop information are squashed to the
same structure ('struct fib6_info'). In order to improve resource
utilization the driver consolidates identical nexthop groups to the same
internal representation of a nexthop group.

Therefore, when the offload indication of a nexthop changes, the driver
needs to iterate over all the linked fib6_info and toggle their offload
flag accordingly.

During abort, all the routes are removed from the device and unlinked
from their nexthop group. The offload indication is cleared just before
the group is destroyed, but by that time no fib6_info is linked to the
group and the offload indication remains set.

Fix this by clearing the offload indication just before dropping the
reference from the nexthop.

Fixes: ee5a0448 ("mlxsw: spectrum_router: Set hardware flags for routes")
Reported-by: NAlex Kushnarov <alexanderk@mellanox.com>
Signed-off-by: NIdo Schimmel <idosch@mellanox.com>
Acked-by: NJiri Pirko <jiri@mellanox.com>
Tested-by: NAlex Kushnarov <alexanderk@mellanox.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The driver uses the same table to represent both the main and local
routing tables. Prevent routes in the main table from replacing routes
in the local table to reflect the fact that the local table is consulted
first during lookup.

Fixes: b6a1d871 ("mlxsw: spectrum_router: Start using new IPv4 route notifications")
Fixes: dacad7b3 ("mlxsw: spectrum_router: Start using new IPv6 route notifications")
Signed-off-by: NIdo Schimmel <idosch@mellanox.com>
Acked-by: NJiri Pirko <jiri@mellanox.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This matches /sys/devices/.../spi1.0/modalias content.

Fixes: 9b2d9f05 ("net: dsa: microchip: add ksz9567 to ksz9477 driver")
Fixes: d9033ae9 ("net: dsa: microchip: add KSZ8563 compatibility string")
Fixes: 8c29bebb ("net: dsa: microchip: add KSZ9893 switch support")
Fixes: 45316818 ("net: dsa: add support for ksz9897 ethernet switch")
Fixes: b987e98e ("dsa: add DSA switch driver for Microchip KSZ9477")
Signed-off-by: NRazvan Stefanescu <razvan.stefanescu@microchip.com>
Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>