[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Original change 594b237b ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are sharing the
same PHY output. Toggle dpms off for one of the stream doesn't power
off the PHY due to the presence of other streams.
2. enable stream failure scenario, where enable stream fails due to
failure of link training. This will cause DPMS off is set to false, while
the actual PHY power state is off in certain cases.
Due to the problematic assumption, the logic will skip disabling
other streams for MST multiple stream scenario, therefore PHY is
not actually powered off.

[how]
1. Rework this refactor by moving PHY state update down to hardware
level, where we update PHY state in place when hardware sequencer
is actually changing the power state of the PHY hardware.
2. Reimplement symclk on TX off workaround in place when we are actually
calling transmitter control to power off PHY in dcn32. Note the workaround is
added due to the lack of proper software interface to set TX while keeping
symclk on. We plan to address this interface problem so we can set TX off
only without affecting symclk in future dcn versions.

Fixes: 594b237b ("drm/amd/display: Add interface to track PHY state")
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
- Pipe split prediction previously only took into
account MPC split. We must also consider when
ODM combine is required, and when we apply ODM
combine by policy.

- Also re-work DET allocation function as it wasn't
properly splitting the DET per stream, per plane.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
After reg offset initialization was switched to runtime rather than
compile time, some of the defintions are not needed anymore and can
be removed.
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2179Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68:
WARNING: conversion to bool not needed here

Generated by: scripts/coccinelle/misc/boolconv.cocci
Signed-off-by: NYihao Han <hanyihao@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drm/amd/display: make optc32_phantom_crtc_post_enable, optc32_setup_manual_trigger and optc32_set_drr static

These three functions are not used outside the function
dcn32_optc.c, so the modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning: no previous prototype for function 'optc32_phantom_crtc_post_enable'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:218:6: warning: no previous prototype for ‘optc32_set_drr’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:193:6: warning: no previous prototype for ‘optc32_setup_manual_trigger’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2140Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These functions are not used outside the file dcn32_dccg.c, so the
modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:257:6: warning: no previous prototype for ‘dccg32_otg_drop_pixel’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:248:6: warning: no previous prototype for ‘dccg32_otg_add_pixel’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:211:6: warning: no previous prototype for ‘dccg32_set_dpstreamclk’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:136:6: warning: no previous prototype for ‘dccg32_set_dtbclk_dto’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2142Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These functions are not used outside the file dcn32_hubbub.c, so the
modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:912:6: warning: no previous prototype for ‘hubbub32_force_wm_propagate_to_pipes’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:823:6: warning: no previous prototype for ‘hubbub32_wm_read_state’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:772:6: warning: no previous prototype for ‘hubbub32_init_watermarks’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:712:6: warning: no previous prototype for ‘hubbub32_force_usr_retraining_allow’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2141Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This symbol is not used outside of dcn32_mmhubbub.c, so marks it static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mmhubbub.c:103:6: warning: no previous prototype for ‘mmhubbub32_config_mcif_buf’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2145Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These two functions are not used outside the function dcn32_mpc.c, so the
modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:704:6: warning: no previous prototype for ‘mpc32_program_shaper’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:900:6: warning: no previous prototype for ‘mpc32_program_3dlut’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2115Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drm/amd/display: make dcn32_link_encoder_is_in_alt_mode and dcn32_link_encoder_get_max_link_cap static

These two functions are not used outside the function
dcn32_dio_link_encoder.c, so the modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dio_link_encoder.c:121:6: warning: no previous prototype for ‘dcn32_link_encoder_is_in_alt_mode’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dio_link_encoder.c:136:6: warning: no previous prototype for ‘dcn32_link_encoder_get_max_link_cap’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2117Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This symbol is not used outside of dcn32_dpp.c, so marks it static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dpp.c:34:6: warning: no previous prototype for ‘dscl32_calc_lb_num_partitions’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2118Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This symbol is not used outside of dcn32_dio_stream_encoder.c, so marks
it static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dio_stream_encoder.c:63:6: warning: no previous prototype for ‘enc32_stream_encoder_dvi_set_stream_attribute’.

Link:https://bugzilla.openanolis.cn/show_bug.cgi?id=2119Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Fix the instatiation sequence for MPC registers and add a few other
missing register definitions that were ommited erroneously when copying
them over to enable runtime initialization of reigster offsets for
DCN32/321
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Kernel does not have a means to tell the userspace to use software
cursor. Due to lack of this functionality, reducing the max cursor size
is the only way to ensure that power savings of Subview port feature is
utilized for asics that support it. The workaround could be removed
after cursor caching is fixed while a subviewport config is active.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Regkey option for forcing num ways for subvp for debug purposes
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
In some cases the viewport position of the main pipes can change without
triggering a full update. In this case the subvp phantom viewports must
be updated accordingly.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
When calculating cursor size for MALL allocation, the cursor width should
be the actual width rounded up to 64 alignment. Additionally, the bit
depth should vary depending on color format.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Leverage SW cursor fall back for SubVP when the cursor is too big. We
want to take advantage of being able to fallback to SW cursor when
possible because it's not worth it to disable MCLK switching because the
cursor is slightly too big.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Update MBLK calculation according to hardware doc.  For DCC case we were
not allocation enough MALL due to an inaccurate MBLK calculation.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
I2C register name starts with 1, unlike other registers that start with
0. This creates a problem with the new register macro refactoring when
I2C HW objects are created in an array.

[How]
Correct I2C register offset by making a new macro to account for array
offset.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NChris Park <chris.park@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
update header files, and remove not used register access marco
Reviewed-by: NHansen Dsouza <hansen.dsouza@amd.com>
Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The indentation of statements in the same curly bracket should be
consistent.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Function wasn't returning false when it had a no stream

[HOW]
Made it return false when it had no stream.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NEthan Wellenreiter <Ethan.Wellenreiter@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
This reverts commit e6cf22ef since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"

Fixes: e6cf22ef ("drm/amd/display: program k1/k2 divider for virtual signal for DCN32")
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.

Prevent entering SS if we are on the edge case and cursor caching is not
possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the
cursor size calculation out of if condition since cursor address may not
be set on all platforms
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For calculating cursor size allocation, surface size was used, resulting
in over allocation
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.

[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR = 1.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NWang Fudong <Fudong.Wang@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.

Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.

[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.
Reviewed-by: NAriel Bernstein <Eric.Bernstein@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Sometimes pixel clock needs to remain active after transmitter disable.

[How]
Use update_phy_state to track PHY state after stream
enable/disable and program pixel clock as needed.
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Refcount is incremented on allocation and
when adding to the context. Therefore we must
release the phantom plane and stream after
removing from the context.
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
When using IGT, kms_bw multi display tests trigger an assert since
we ignore virtual signal type. k1/k2 dividers should be correctly
programmed if VSYNC needs to be correct. Add the appropriate condition
to the if arm to fix this.
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DC was using compile time initialization of register addresses using
SR_* macros and their variants. These have been converted to use runtime
initialization.

The REG_STRUCT macro is a definition that is added to SR_* macros.
During initialization, this must be defined before SR_* macros are
invoked, which are in turn invoked through various IP initialization macros.
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Reprogramming the stream despite no changes in ODM combine mode.
Reprogramming the stream would cause intermittent black screen on
display which could only be recovered through enable/disable sequence.

[HOW]
Fixed bug where we detected a change in ODM combine mode despite ODM
combine mode being disabled. Also removed code which required stream to
be reprogrammed once a change in ODM combine mode was noticed. Lastly we
do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32,
therefore we never want to change its ODM policy.
Reviewed-by: NSamson Tam <Samson.Tam@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Use pitch when calculating size to cache in MALL
Reviewed-by: NSamson Tam <Samson.Tam@amd.com>
Acked-by: NBrian Chang <Brian.Chang@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>