drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch converts the code to use rational best approximation algorithm which
is much more precise.
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it
will be switched to rational base approximation algorithm.
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The patch adds mwidth and nwidth fields to the struct clk_fractional_divider
for further usage. While here, use GENMASK() instead of open coding this
functionality.
Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Rename function parameter to be more explicit what it is for. This also makes
it in align with struct clk_ops.

There is no functional change.
Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the master IP module, and the offset from the master IP module's
base address. A value of 0 is perfectly valid, and the current error
checking will fail in these cases. The issue was found when trying
to enable the iva2_ck clock on OMAP3 platforms.

So, switch the check to use IS_ERR. This correction is similar to the
logic used in commit c807dbed ("clk: ti: fix ti_clk_get_reg_addr
error handling").

Fixes: 9f37e90e ("clk: ti: dflt: move support for default gate clock..")
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.

This solves the following oops:

[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c

Fixes: aafd900c ("CLK: TI: add omap3 clock init file")
Cc: stable@vger.kernel.org
Cc: mturquette@baylibre.com
Cc: sboyd@codeaurora.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@lists.codethink.co.uk
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.

Fixes: a74c52de ("clk: ti: clk-7xx: Correct ABE DPLL configuration")
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

This simplifies the given function by getting rid of the manual
sign extension as well as saving an absolute value in an extra
variable.
Signed-off-by: NMartin Kepplinger <martink@posteo.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

mmc host controller's IO input/output timing is unpredictable if
bootloader execute tuning for HS200 mode. It might make kernel failed
to initialize mmc card in identification mode. The root cause is
tuning phase and degree setting for HS200 mode in bootloader aren't
applicable to that of identification mode in kernel stage. Anyway, we
can't force all bootloaders to reset tuning phase and degree setting
before into kernel. Simply reset it in rockchip_clk_register_mmc.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad
result. The division before multiplication computes a wrong value ; the
calculation is inverted to fix the problem. The second issue is that the exact
rate have decimals and they are truncate. The consequence is that the function
clk_frac_set_rate (which use the result of clk_frac_round_rate) computes a
wrong value for the register (the rate generated can be closer to the desired
rate). The correction is : if there is decimal to the result, it is rounded to
the next larger integer.
On drivers/clk/mxs/clk-frac.c, the function clk_frac_recalc_rate returned
a bad result. The multiplication is made before the division to compute a
correct value.
Signed-off-by: NVictorien Vedrine <victorien.vedrine@ophrys.net>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The function can return negative value.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Separate the update of pll registers from the actual set_rate function
so that the init callback does not need to access clk-API functions.

As we now have separated the getting and setting of the pll parameters
we can also directly use these new functions in other places too.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents can generate divided rates.
This would allow a peripheral to have finer grained clocks for generating
a baud rate, clocking an asynchronous part or having more
options in frequency.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
[sboyd@codeaurora.org: Transition to new clk_hw provider APIs]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the new sama5d2 SoC and adapt capabilities.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

As some more information is added to the PCR register, we'd better use
a copy of its content and modify just the peripheral-related bits.
Implement a read-modify-write for the enable() and disable() callbacks.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add _MASK and _OFFSET values and cleanup register fields layout.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.

dpi_ck was removed due to no clock reference to it.

Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device tree.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

Remove unused header files from MT8173, and remove unused
keywords from function declaration.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>

Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>

Power management on of NoC(Notwork On Chip) requires that disconnect
and reconnect routine should been done during clk disable/enable.

also there are different types of clocks,
For NoC Macro clocks, write idle_bit and wait for hardward ACK;
For Socket clocks, write idle_bit;
For others, do nothing.
Signed-off-by: NGuo Zeng <Guo.Zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

re-order the codes more reasonable by moving variable-definition
together.
Signed-off-by: NGuo Zeng <Guo.Zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
incorrectly used as a bit numbers.  Fix it.

Tested on Exynos4210 based Origen board and on Exynos5250 based
Arndale board.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Fixes: ddeac8d9 ("clk: samsung: add infrastructure to register cpu clocks")
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the msm8916 audio clocks. This includes core bus,
low-power audio and codec clocks. They are required for audio playback.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the msm8916 BIMC (Bus Integrated Memory Controller)
clocks that are needed for GPU.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some root clock generators may have child branches that are controlled
by different CPUs. These RCGs require some special operations:
 - some enable bits have to be toggled when we set the rate;
 - if RCG is disabled we only cache the rate and set it later when enabled;
 - when the RCG is disabled, the mux is set to the safe source;
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
[sboyd@codeaurora.org: Simplify recalc_rate implementation]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the msm8916 TCU (Translation Control Unit) clocks that
are needed for IOMMU.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use a generic name for this kind of PLL

Correction in dts files are already done here:
commit 5eb26c60 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There are cleary typo errors so can be removed.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Acked-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

If a mux clock is initialised (by hardware or firmware) with an
invalid parent, its ->get_parent() can return an out of range
index.  For example, the generic mux clock attempts to return
-EINVAL, which due to the u8 return type ends up a rather large
number.  Using this index with the parent_names[] array results
in an invalid pointer and (usually) a crash in the following
strcmp().

This patch adds a check for the parent index being in range,
ignoring clocks reporting invalid values.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Tested-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: NStephane Viau <sviau@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There's just one GDSC as part of the msm8974 GCC block.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>