- 16 5月, 2015 1 次提交
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由 Brian Norris 提交于
In commit 8ff16cf7 ("Documentation: devicetree: m25p80: add "nor-jedec" binding"), we added a generic "nor-jedec" binding to catch all mostly-compatible SPI NOR flash which can be detected via the READ ID opcode (0x9F). This was discussed and reviewed at the time, however objections have come up since then as part of this discussion: http://lkml.kernel.org/g/20150511224646.GJ32500@ld-irv-0074 It seems the parties involved agree that "jedec,spi-nor" does a better job of capturing the fact that this is SPI-specific, not just any NOR flash. This binding was only merged for v4.1-rc1, so it's still OK to change the naming. At the same time, let's move the documentation to a better name. Next up: stop referring to code (drivers/mtd/devices/m25p80.c) from the documentation. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NMark Rutland <mark.rutland@arm.com>
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- 07 5月, 2015 1 次提交
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由 Rafał Miłecki 提交于
We had many entries that were recently added just to allow selecting some flashes directly but were never used. They weren't providing any special flash handling, we just needed them due to the lack of some generic binding string. With the introduction of "nor-jedec" (in 1103b851) they won't be needed unless we discover some faulty flash requiring workarounds. As explained in m25p80 DT documentation we require specifying "nor-jedec" now as less specific compatible entry. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 06 4月, 2015 1 次提交
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由 Brian Norris 提交于
Use the new 'nor-jedec' binding to provide automatic detection of flash that use the 0x9F READ ID opcode. This can help for use cases where platforms just specify compatibility with "m25p80", and then see messages like this: m25p80 spi32766.0: found s25fl256s1, expected m25p80 Instead, they can just specify the generic string and see this: m25p80 spi32766.0: s25fl256s1 (32768 Kbytes) Also, update the language about m25p_ids[] to straighten out the expectations here. We should no longer need to continuously grow the m25p_ids[] table, and in fact, we might want to start removing entries which are not used in device trees so far, so we can just default to auto-detection as much as possible in the future. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com>
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- 01 12月, 2014 1 次提交
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由 Brian Norris 提交于
write_enable() was being duplicated to both m25p80.c and fsl-quadspi.c. But this should be handled within the spi-nor abstraction layer. At the same time, let's add write_disable() after erasing, so we don't leave the flash in a write-enabled state afterward. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NHuang Shijie <shijie.huang@intel.com>
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- 26 11月, 2014 2 次提交
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由 Knut Wohlrab 提交于
Signed-off-by: NKnut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: NAlison Chaiken <alison_chaiken@mentor.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Alison Chaiken 提交于
As stated in a5b7616c, "mtd: m25p80,spi-nor: Fix module aliases for m25p80", m25p_ids[] in m25p80.c needs to be kept in sync with spi_nor_ids[] in spi-nor.c. The change here corrects a misalignment. (We were missing m25px80 and we had a duplicate w25q128.) Signed-off-by: NAlison Chaiken <alison_chaiken@mentor.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: <stable@vger.kernel.org> # 3.18+
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- 05 11月, 2014 2 次提交
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由 Brian Norris 提交于
spi-nor.c should be taking care of these now. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NMarek Vasut <marex@denx.de>
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由 Huang Shijie 提交于
For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8. The dummy cycles is actually 8 for SPI fast/dual/quad read. This patch makes preparations for the DDR quad read, it fixes the wrong dummy value for both the spi-nor.c and m25p80.c. Signed-off-by: NHuang Shijie <b32955@freescale.com> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 22 10月, 2014 1 次提交
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由 Ben Hutchings 提交于
m25p80's device ID table is now spi_nor_ids, defined in spi-nor. The MODULE_DEVICE_TABLE() macro doesn't work with extern definitions, but its use was also removed at the same time. Now if m25p80 is built as a module it doesn't get the necessary aliases to be loaded automatically. A clean solution to this will involve defining the list of device IDs in spi-nor.h and removing struct spi_device_id from the spi-nor API, but this is quite a large change. As a quick fix suitable for stable, copy the device IDs back into m25p80. Fixes: 03e296f6 ("mtd: m25p80: use the SPI nor framework") Cc: <stable@vger.kernel.org> # 3.16.x: 32f1b7c8: mtd: move support for struct flash_platform_data into m25p80 Cc: <stable@vger.kernel.org> # 3.16.x: 90e55b38: mtd: m25p80: get rid of spi_get_device_id Cc: <stable@vger.kernel.org> # 3.16.x: 70f3ce05: mtd: spi-nor: make spi_nor_scan() take a chip type name, not spi_device_id Cc: <stable@vger.kernel.org> # 3.16.x Signed-off-by: NBen Hutchings <ben@decadent.org.uk> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 18 10月, 2014 2 次提交
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由 Ben Hutchings 提交于
Drivers currently call spi_nor_match_id() and then spi_nor_scan(). This adds a dependency on struct spi_device_id which we want to avoid. Make spi_nor_scan() do it for them. Signed-off-by: NBen Hutchings <ben@decadent.org.uk> Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
This simplifies the way we use spi_nor framework and will allow us to drop spi_nor_match_id. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 29 9月, 2014 1 次提交
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由 Rafał Miłecki 提交于
This "type" seems to be an extra hint for m25p80 about the flash. Some archs register flash_platform_data with "name" set to "m25p80" and then with a real flash name set in "type". It seems to be a trick specific to the m25p80 so let's move it out of spi-nor. Btw switch to the spi_nor_match_id instead of iterating spi_nor_ids. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 13 5月, 2014 1 次提交
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由 Geert Uytterhoeven 提交于
Commit 03e296f6 ("mtd: m25p80: use the SPI nor framework") accidentally removed support for Dual SPI read transfers. Add it back. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NHuang Shijie <shijie8@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 15 4月, 2014 2 次提交
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由 Brian Norris 提交于
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NMarek Vasut <marex@denx.de> Acked-by: NHuang Shijie <b32955@freescale.com>
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由 Brian Norris 提交于
Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: NHuang Shijie <b32955@freescale.com> Acked-by: NMarek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 11 3月, 2014 6 次提交
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由 Brian Norris 提交于
Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Kuninori Morimoto 提交于
Signed-off-by: NYusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Axel Lin 提交于
For slightly better readability. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Paul Gortmaker 提交于
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> [Brian: dropped one incorrect hunk] Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Geert Uytterhoeven 提交于
Spansion s25fl256s1 and s25fl512s support Dual SPI transfers, hence set the M25P80_DUAL_READ flag. Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Geert Uytterhoeven 提交于
Add support for Dual SPI read transfers, which is supported by some Spansion SPI FLASHes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 28 1月, 2014 2 次提交
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由 Geert Uytterhoeven 提交于
When using the Quad Read opcode, SPI masters still use Single SPI transfers, as spi_transfer.rx_nbits defaults to SPI_NBITS_SINGLE. Use SPI_NBITS_QUAD to fix this. While an earlier version of commit 3487a639 ("drivers: mtd: m25p80: add quad read support") did this correctly, it was forgotten in the version that got merged. Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Geert Uytterhoeven 提交于
Spansion s25fl512s supports Quad SPI transfers, hence set the M25P80_QUAD_READ flag. Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 21 1月, 2014 1 次提交
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由 Brian Norris 提交于
In the following commit (in -next): commit 8552b439 drivers: mtd: m25p80: convert "bool" read check into an enum We converted the boolean 'fast_read' property to become an enum 'flash_read', but at the same time, we changed the conditional path so that it doesn't choose a default value in some cases (technically, we choose the correct default simply by virtue of devm_kzalloc(), which zeroes this out to be a NORMAL read operation, but still...). Fix this by setting a default for the 'else' clause. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Acked-by: NMarek Vasut <marex@denx.de>
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- 17 1月, 2014 1 次提交
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由 Geert Uytterhoeven 提交于
commit 3487a639 ("drivers: mtd: m25p80: add quad read support") in -next added both the 3-byte OPCODE_QUAD_READ and the 4-byte OPCODE_QUAD_READ_4B, but incorrectly uses OPCODE_QUAD_READ for both 3-byte and 4-byte addressing. Use OPCODE_QUAD_READ_4B in the 4-byte case to fix this. Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 04 1月, 2014 3 次提交
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由 Igor Grinberg 提交于
Add support for Micron m25px16 spi flash chip. Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Sourav Poddar 提交于
Some flash also support quad read mode. Adding support for quad read mode in m25p80 for Spansion and Macronix flash. [Tweaked by Brian] With this patch, quad-read support will override fast-read and normal-read, if the SPI controller and flash chip both support it. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Reviewed-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Sourav Poddar 提交于
This is a cleanup prior to adding quad read support. This will facilitate easy addition of more read commands check under an enum rather that defining a separate bool for it. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 07 11月, 2013 8 次提交
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由 Brian Norris 提交于
Device removal should fail if MTD unregistration fails. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NMarek Vasut <marex@denx.de>
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由 Brian Norris 提交于
A new 32Mbit SPI NOR flash from Macronix. Nothing special. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NMarek Vasut <marex@denx.de>
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由 Brian Norris 提交于
It seems like the following commit was never necessary commit 5f949137 Author: Shaohui Xie <Shaohui.Xie@freescale.com> Date: Fri Oct 14 15:49:00 2011 +0800 mtd: m25p80: don't probe device which has status of 'disabled' because it duplicates the code in of_platform_device_create_pdata() which ensures that 'disabled' nodes are never instantiated. Also, drop the __maybe_unused. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NSourav Poddar <sourav.poddar@ti.com> Reviewed-by: NGrant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: <devicetree@vger.kernel.org>
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由 Brian Norris 提交于
Remove the compile-time option for FAST_READ, since we have run-time support for detecting it. This refactors the logic for enabling fast-read, such that for DT-enabled devices, we honor the "m25p,fast-read" property but for non-DT devices, we default to using FAST_READ whenever the flash device supports it. Normal READ and FAST_READ differ only in the following: * FAST_READ supports SPI higher clock frequencies [1] * number of dummy cycles; FAST_READ requires 8 dummy cycles (whereas READ requires 0) to allow the flash sufficient setup time, even when running at higher clock speeds Thus, for flash chips which support FAST_READ, there is otherwise no limiting reason why we cannot use the FAST_READ opcode instead of READ. It simply allows the SPI controller to run at higher clock rates. So theoretically, nobody should be needing the compile-time option anyway. [1] I have a Spansion S25FL128S datasheet which says: "The maximum operating clock frequency for the READ command is 50 MHz." And: "The maximum operating clock frequency for FAST READ command is 133 MHz." Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Brian Norris 提交于
No change in the table data. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NSourav Poddar <sourav.poddar@ti.com>
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由 Brian Norris 提交于
The FIXME and NOTE have already been fixed (we have FAST_READ support). Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NSourav Poddar <sourav.poddar@ti.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Brian Norris 提交于
This patch fixes two memory errors: 1. During a probe failure (in mtd_device_parse_register?) the command buffer would not be freed. 2. The command buffer's size is determined based on the 'fast_read' boolean, but the assignment of fast_read is made after this allocation. Thus, the buffer may be allocated "too small". To fix the first, just switch to the devres version of kzalloc. To fix the second, increase MAX_CMD_SIZE unconditionally. It's not worth saving a byte to fiddle around with the conditions here. This problem was reported by Yuhang Wang a while back. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reported-by: NYuhang Wang <wangyuhang2014@gmail.com> Reviewed-by: NSourav Poddar <sourav.poddar@ti.com> Cc: <stable@vger.kernel.org>
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由 Priyanka Jain 提交于
Micron N25Q512A is a spi flash memory with following features: -64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory. -Memory is organised as 1024(64KB) main sectors. -Each sector is divided into 256 pages. -Register set/Opcodes are similar to other N25Q family products. Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 28 10月, 2013 1 次提交
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由 Flavio Silveira 提交于
This flashchip is used in D-Link DIR-610 A1 router board and maybe several others, yet is not kernel upstream. So add support for it according to datasheet [0], making it easier to support other boards using this flashchip in the future. [0] http://www.esmt.com.tw/DB/manager/upload/F25L32PA.pdfSigned-off-by: NFlavio Silveira <fggs@terra.com.br> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 27 9月, 2013 1 次提交
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由 Elie De Brauwer 提交于
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: NElie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 31 8月, 2013 2 次提交
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由 Michel Stempin 提交于
Add support for PMC (now Chingis, part of ISSI) Pm25LV512 (512 Kib), Pm25LV010 (1 Mib) and Pm25LQ032 (32 Mib) SPI Flash chips. This patch addresses two generations of PMC SPI Flash chips: - Pm25LV512 and Pm25LV010: these have 4KiB sectors and 32KiB blocks. The 4KiB sector erase uses a non-standard opcode (0xd7). They do not support JEDEC RDID (0x9f), and so they can only be detected by matching their name string with pre-configured platform data. Because of the cascaded acquisitions, the datasheet is no longer available on the current manufacturer's website, although it is still commonly used in some recent wireless routers (<https://forum.openwrt.org/viewtopic.php?pid=186360#p186360>). The only public datasheet available seems to be on GeoCities: <http://www.geocities.jp/scottle556/pdf/Pm25LV512-010.pdf> - Pm25LQ032: a newer generation flash, with 4KiB sectors and 64KiB blocks. It uses the standard erase and JEDEC read-ID opcodes. Manufacturer's datasheet is here: <http://www.chingistek.com/img/Product_Files/Pm25LQ032C%20datasheet%20v1.6.1.pdf> This patch is resent in order to take into account both Brian Norris remarks and this upstream patch: commit e534ee4f Author: Krzysztof Mazur <krzysiek@podlesie.net> Date: Fri Feb 22 15:51:05 2013 +0100 mtd: m25p80: introduce SST_WRITE flag for SST byte programming Not all SST devices implement the SST byte programming command. Some devices (like SST25VF064C) implement only standard m25p80 page write command. Now SPI flash devices that need sst_write() are explicitly marked with new SST_WRITE flag and the decision to use sst_write() is based on this flag instead of manufacturer id. Signed-off-by: NGabor Juhos <juhosg@openwrt.org> Signed-off-by: NMichel Stempin <michel.stempin@wanadoo.fr> [Brian: fixed conflict] Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Markus Niebel 提交于
This adds support for the Everspin mr25h10 MRAM chip to the m25p80 driver. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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