- 17 7月, 2021 3 次提交
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由 Kurt Kanzenbach 提交于
Each i225 has three LEDs. Export them via the LED class framework. Each LED is controllable via sysfs. Example: $ cd /sys/class/leds/igc_led0 $ cat brightness # Current Mode $ cat max_brightness # 15 $ echo 0 > brightness # Mode 0 $ echo 1 > brightness # Mode 1 The brightness field here reflects the different LED modes ranging from 0 to 15. Signed-off-by: NKurt Kanzenbach <kurt@linutronix.de> Reviewed-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Kurt Kanzenbach 提交于
Use the flex filter mechanism to extend the current ethtool filter operations by intercoperating the user data. This allows to match eight more bytes within a Ethernet frame in addition to macs, ether types and vlan. The matching pattern looks like this: * dest_mac [6] * src_mac [6] * tpid [2] * vlan tci [2] * ether type [2] * user data [8] This can be used to match Profinet traffic classes by FrameID range. Signed-off-by: NKurt Kanzenbach <kurt@linutronix.de> Reviewed-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Kurt Kanzenbach 提交于
The Intel i225 NIC has the possibility to add flex filters which can match up to the first 128 byte of a packet. These filters are useful for all kind of packet matching. One particular use case is Profinet, as the different traffic classes are distinguished by the frame id range which cannot be matched by any other means. Add code to configure and enable flex filters. Signed-off-by: NKurt Kanzenbach <kurt@linutronix.de> Reviewed-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NVinicius Costa Gomes <vinicius.gomes@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 05 6月, 2021 3 次提交
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Add HW VLAN acceleration protocol handling. In case of HW VLAN tagging, we need that protocol available in the ndo_start_xmit(), so that it will be stored in a new fields in the skb. HW offloading is set to OFF by default. Users are allow to turn on/off Rx/Tx HW VLAN acceleration via ethtool. Signed-off-by: NMuhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Acked-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
Minor fix of indentation in igc_defines.h Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
The CR_1000T_ASYM_PAUSE bit from igc defines is not used so remove it. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 17 4月, 2021 1 次提交
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由 Ederson de Souza 提交于
The i225 device offers a number of special PTP Hardware Clock features on the Software Defined Pins (SDPs) - much like i210, which is used as inspiration for this patch. It enables two possible functions, namely time stamping external events and periodic output signals. The assignment of PHC functions to the four SDP can be freely chosen by the user. For the external events time stamping, when the SDP (configured as input by user) level changes, an interrupt is generated and the kernel Precision Time Protocol (PTP) is informed. For the periodic output signals, the i225 is configured to generate them (so the SDP level will change periodically) and the driver also has to keep updating the time of the next level change. However, this work is not necessary for some frequencies as the i225 takes care of them (namely, anything with a half-cycle of 500ms, 250ms, 125ms or < 70ms). While i225 allows up to four timers to be used to source the time used on the external events or output signals, this patch uses only one of those timers. Main reason is to keep it simple, as it's not clear how these extra timers would be exposed to users. Note that currently a NIC can expose a single PTP device. Signed-off-by: NEderson de Souza <ederson.desouza@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 20 3月, 2021 3 次提交
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由 Sasha Neftin 提交于
MII_CR_LOOPBACK masks not in use in i225 device and can be removed. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
Force PHY speed not supported for i225 devices. MII_CR_SPEED masks not in use in i225 device and can be removed. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
MII_CR_RESET mask not in use in i225 device and can be removed Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NDvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 04 2月, 2021 4 次提交
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由 Sasha Neftin 提交于
FUNC_1 mask not in use in i225 device and could be removed Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
Local receiver mask SR_1000T_LOCAL_RX_STATUS not in use in i225 device and could be removed Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
Expose the NVM map version via drvinfo in ethtool NVM image version is reported as firmware version for i225 device Minor typo fix - remove space Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Sasha Neftin 提交于
Multiple Tx Data Read Requests is hardware pipeline feature and is not controlled by software Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 29 9月, 2020 2 次提交
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由 Andre Guedes 提交于
i225 advanced receive descriptor doesn't have the following extend error bits: CE, SE, SEQ, CXE. In addition to that, the bit TCPE is called L4E in the datasheet. Clean up the code accordingly, and get rid of the macro IGC_RXDEXT_ERR_FRAME_ERR_MASK since it doesn't make much sense anymore. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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由 Andre Guedes 提交于
Rename the IGC_TSYNCTXCTL_VALID macro to IGC_TSYNCTXCTL_TXTT_0 so it matches the datasheet. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
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- 30 6月, 2020 3 次提交
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由 Andre Guedes 提交于
Differently from I210, I225 doesn't report Rx timestamps via the TS bit Rx descriptor + RXSTMPL/RXSTMPH registers mechanism. Rx timestamps are reported in the packet buffer only, which is implemented by igc_ptp_rx_ pktstamp(). So this patch removes igc_ptp_rx_rgtstamp() and all code related to it, copied from igb driver. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
The LTR message on the PCIe inform the requested latency on which the PCIe must become active to the downstream PCIe port of the system. This patch provide recommended LTR parameters by i225 specification. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
IEEE802.3az-2010 Energy Efficient Ethernet has been approved as standard (September 2010) and the driver can enable and disable it via ethtool. Disable the feature by default on parts which support it. Add enable/disable eee options. tx-lpi, tx-timer and advertise not supported yet. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Reviewed-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 29 5月, 2020 1 次提交
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由 Sasha Neftin 提交于
Transmit underrun, late and excess collision flags not in use. This patch comes to clean up these flags. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 23 5月, 2020 1 次提交
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由 Sasha Neftin 提交于
Enable Tidv register, Report Packet Sent, Report Status and Ethernet CRC flags not in use. This patch comes to clean up these flags. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 22 5月, 2020 1 次提交
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由 Andre Guedes 提交于
This patch extends MAC address filter internal APIs igc_add_mac_filter() and igc_del_mac_filter(), as well as local helpers, to support filters based on source address. A new parameters 'type' is added to the APIs to indicate if the filter type is source or destination. In case it is source type, the RAH register is configured accordingly in igc_set_mac_filter_hw(). Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 21 5月, 2020 1 次提交
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由 Andre Guedes 提交于
In igc_adapter we keep a sort of shadow copy of RAL and RAH registers. There is not much benefit in keeping it, at the cost of maintainability, since adding/removing MAC address filters is not hot path, and we already keep filters information in adapter->nfc_filter_list for cleanup and restoration purposes. So in order to simplify the MAC address filtering code and prepare it for source address support, this patch removes the mac_table from igc_adapter. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 20 5月, 2020 4 次提交
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由 Sasha Neftin 提交于
Device reset assert for interrupt cause register not in use for i225 device. This patch comes to clean up this define. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Andre Guedes 提交于
The driver only supports hardware timestamping for all incoming traffic (HWTSTAMP_FILTER_ALL) which is enabled via Rx Time Sync Control (TSYNCRXCTL) register already. Therefore, the ethertype filter set in in igc_ptp_set_timestamp_mode() is useless so this patch removes it. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Andre Guedes 提交于
This patch renames the IGC_VLAPQF macro to IGC_VLANPQF as well as related macros so they match the register name and fields described in the data sheet. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
Packet buffer allocation, reserved word and pointer guard not applicable for i225 parts. This patch comes to clean up these obsolete defines Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 19 5月, 2020 1 次提交
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由 Sasha Neftin 提交于
PHY_FORCE_LIMIT definition not in use and could be removed i225 parts support auto negotiation mechanism Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 18 4月, 2020 6 次提交
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由 Andre Guedes 提交于
The support for ethtool Network Flow Classification (NFC) queue redirection based on destination MAC address is currently broken in IGC. For instance, if we add the following rule, matching frames aren't enqueued on the expected rx queue. $ ethtool -N IFNAME flow-type ether dst 3c:fd:fe:9e:7f:71 queue 2 The issue here is due to the fact that igc_rar_set_index() is missing code to enable the queue selection feature from Receive Address High (RAH) register. This patch adds the missing code and fixes the issue. Signed-off-by: NAndre Guedes <andre.guedes@intel.com> Acked-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
i225 device support copper mode only PHY signal detect indication for copper fiber switch not applicable to i225 part Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
We support only copper mode Not applicable for i225 parts Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
Formally Destination bit should be kept reserved to support legacy drivers and ignore on write/read operation Not applicable for i225 parts Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Vinicius Costa Gomes 提交于
This adds support for ETF offloading for the i225 controller. For i225, the LaunchTime feature is almost a subset of the Qbv feature. The main change from the i210 is that the launchtime of each packet is specified as an offset applied to the BASET register. BASET is automatically incremented each cycle. For i225, the approach chosen is to re-use most of the setup used for taprio offloading. With a few changes: - The more or less obvious one is that when ETF is enabled, we should set add the expected launchtime to the (advanced) transmit descriptor; - The less obvious, is that when taprio offloading is not enabled, we add a dummy schedule (all queues are open all the time, with a cycle time of 1 second). Signed-off-by: NVinicius Costa Gomes <vinicius.gomes@intel.com> Reviewed-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Vinicius Costa Gomes 提交于
Adds support for translating taprio schedules into i225 cycles. This will allow schedules to run in the hardware, making the schedules enforcement more precise and saving CPU time. Right now, the only simple schedules are allowed, complex schedules are rejected. "simple" in this context are schedules that each HW queue is opened and closed only once in each cycle. Changing schedules is still not supported as well. Signed-off-by: NVinicius Costa Gomes <vinicius.gomes@intel.com> Reviewed-by: NAndre Guedes <andre.guedes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 20 2月, 2020 2 次提交
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由 Sasha Neftin 提交于
This patch adds a define and WOL support for an i225 parts. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
Placeholder for debugging functionality. In this patch, we add some registers and rings summary dumps. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 18 1月, 2020 2 次提交
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由 Sasha Neftin 提交于
PHY power management control should provide a reliable and accurate indication of PHY reset completion and decrease the delay time after a PHY reset Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Sasha Neftin 提交于
TCP segmentation offload allows a device to segment a single frame into multiple frames with a data payload size specified in socket buffer. As a result we can now send data approximately up to seven percents fast than was previously possible on my system. Signed-off-by: NSasha Neftin <sasha.neftin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 07 1月, 2020 2 次提交
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由 Vinicius Costa Gomes 提交于
For better accuracy, i225 is able to do timestamping using the Start of Packet signal from the PHY. Signed-off-by: NVinicius Costa Gomes <vinicius.gomes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Vinicius Costa Gomes 提交于
This adds support for timestamping packets being transmitted. Based on the code from i210. The basic differences is that i225 has 4 registers to store the transmit timestamps (i210 has one). Right now, we only support retrieving from one register, support for using the other registers will be added later. Signed-off-by: NVinicius Costa Gomes <vinicius.gomes@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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