Hard to follow who is pointing what to where and why so it's simply getting
in the way of the time code renovation.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAhmed S. Darwish <darwish.07@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This has not been any serious user of this ill conceived thing since the
original invention in like '95.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

early_serial_setup was removed from serial.h, but forgot to put in
serial_8250.h
Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Patch to add PCI support for the PMC-Sierra MSP71xx devices.
Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Patch to add core platform support for the PMC-Sierra MSP71xx devices.
Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Serial driver patch for the PMC-Sierra MSP71xx devices.

There are three different fixes:

1 Fix for DesignWare APB THRE errata: In brief, this is a non-standard
  16550 in that the THRE interrupt will not re-assert itself simply by
  disabling and re-enabling the THRI bit in the IER, it is only re-enabled
  if a character is actually sent out.

  It appears that the "8250-uart-backup-timer.patch" in the "mm" tree
  also fixes it so we have dropped our initial workaround.  This patch now
  needs to be applied on top of that "mm" patch.

2 Fix for Busy Detect on LCR write: The DesignWare APB UART has a feature
  which causes a new Busy Detect interrupt to be generated if it's busy
  when the LCR is written.  This fix saves the value of the LCR and
  rewrites it after clearing the interrupt.

3 Workaround for interrupt/data concurrency issue: The SoC needs to
  ensure that writes that can cause interrupts to be cleared reach the UART
  before returning from the ISR.  This fix reads a non-destructive register
  on the UART so the read transaction completion ensures the previously
  queued write transaction has also completed.
Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>