When booting with device tree static clkdev aliases should not be used.
This patch modifies the samsung_pwm_timer driver to use DT-based clock
lookup when booting with device tree.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The Armada XP timer has two mandatory clock inputs: nbclk and refclk,
as specified by the device-tree binding.

This commit fixes the clock selection. Instead of hard-coding the clock
rate for the 25 MHz reference fixed-clock, obtain the clock by its name.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

If the clock fails to be obtained and the timer fails to be properly
registered, the kernel will freeze real soon. Instead, let's BUG()
where the actual problem is located.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The Armada XP SoC clocksource driver cannot work without the 25 MHz
fixed timer. Therefore it's appropriate to introduce a new compatible
string and use it to set the 25 MHz fixed timer.

The 'marvell,timer-25MHz' property will be marked as deprecated.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>

This is almost cosmetic: we achieve a bit of consistency with
other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE
macro for the boilerplate code.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>

This commit creates two functions to access the TIMER_CTRL register:
one for global one for the per-cpu. This makes the code much more
readable. In addition, since the TIMER_CTRL register is also used for
watchdog, this is preparation work for future thread-safe improvements.
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This is a purely cosmetic commit: we replace hardcoded values that
representing bits by BIT(), which is slightly more readable.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>

Using 0x%# emits 0x0x.  Only one is necessary.
Signed-off-by: NJoe Perches <joe@perches.com>
Acked-by: NTakashi Iwai <tiwai@suse.de>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Add the dynamic irq affinity feature to the timer clock device.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NVincent Guittot <vincent.guittot@linaro.org>
Acked-by: NRickard Andersson <rickard.andersson@stericsson.com>

Add support for CMT hardware with 32-bit control and counter
registers, as found on r8a73a4 and r8a7790. To use the CMT
with 32-bit hardware a second I/O memory resource needs to
point out the CMSTR register and it needs to be 32 bit wide.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Reviewed-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace kzalloc, clk_get, ioremap and request_irq by their managed
counterparts to simplify error paths.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

[ this is a follow-up to this discussion:
http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ]
This patchset renames all uses of "bcm," name bindings to
"brcm," as they were done prior to knowing that brcm had
already been standardized as Broadcom vendor prefix
(in Documentation/devicetree/bindings/vendor-prefixes.txt).
This will not cause any churn on devices because none of
these bindings have made it into production yet.
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Current suspend/resume handling of the driver was broken, because:
 - periodic timer was being enabled in CLOCK_EVT_MODE_RESUME mode, which
   does not seem to be correct behavior looking at other platforms,
 - PWM divisors need to be restored, but they were not,
 - clockevent interrupt mask needs to be restored, but it was not,
 - clocksource was being restored in clockevent resume callback.

This patch fixes issues mentioned above, making suspend/resume handling
in the driver correct.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Brown <broonie@linaro.org>
Tested-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In case of Samsung PWM timer, clocksource MMIO can not be used, because
custom suspend/resume callbacks are required.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Brown <broonie@linaro.org>
Tested-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Instead of calculating register every time the timer should be read,
we can just do it one time at initialization and store the address in
driver data.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Brown <broonie@linaro.org>
Tested-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

PWM channel 4 has its autoreload bit located at different position. This
patch fixes the driver to account for that.

This fixes a problem with the clocksource hanging after it overflows because
it is not reloaded any more.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Brown <broonie@linaro.org>
Tested-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

PWM registers are shared between clocksource and PWM drivers and so can
not be claimed for exclusive use.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Brown <broonie@linaro.org>
Tested-by: NSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add support for the memory mapped timers by filling in the
read/write functions and adding some parsing code. Note that we
only register one clocksource, preferring the cp15 based
clocksource over the mmio one.

To keep things simple we register one global clockevent. This
covers the case of UP and SMP systems with only mmio hardware and
systems where the memory mapped timers are used as the broadcast
timer in low power modes.

The DT binding allows for per-CPU memory mapped timers in case we
want to support that in the future, but the code isn't added
here. We also don't do much for hypervisor support, although it
should be possible to support it by searching for at least two
frames where one frame has the virtual capability and then
updating KVM timers to support it.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>

We're going to introduce support to read and write the memory
mapped timer registers in the next patch, so push the cp15
read/write functions one level deeper. This simplifies the next
patch and makes it clearer what's going on.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>

There isn't any reason why we don't pass the event here and we'll
need it in the near future for memory mapped arch timers anyway.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>

Using an enum for the register we wish to access allows newer
compilers to determine if we've forgotten a case in our switch
statement. This allows us to remove the BUILD_BUG() instances in
the arm64 port, avoiding problems where optimizations may not
happen.

To try and force better code generation we're currently marking
the accessor functions as inline, but newer compilers can ignore
the inline keyword unless it's marked __always_inline. Luckily on
arm and arm64 inline is __always_inline, but let's make
everything __always_inline to be explicit.
Suggested-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>

bitops.h included implicitly, add #include <linux/bitops.h>
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch adds an clocksource driver for the main timer(s)
found on MOXA ART SoCs.

The MOXA ART SoC provides three separate timers with individual
count/load/match registers, two are used here:

TIMER1: clockevents, used to support oneshot and periodic events
TIMER2: set up as a free running counter, used as clocksource

Timers are preconfigured by bootloader to count down and interrupt
on match or zero. Count increments every APB clock cycle and is
automatically reloaded when it reaches zero.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Reuse the TTC clocksource timer as sched clock provider.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <monstr@monstr.eu>

The clk-provider.h header is not required by this driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The interval was firing at was set up at probe time, and only changed in
the set_next_event, and never changed back, which is not really what is
expected.

When enabling the periodic mode, now set an interval to tick every
jiffy.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current bring-up code for the timer was overly complicated. The only
thing we need is actually which clock we want to use as source and
that's pretty much all. Let's keep it that way.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The prescaler is only used when using the internal low frequency
oscillator (at 32kHz). Since we're using the higher frequency oscillator
at 24MHz, we can just remove it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The set_next_event and set_mode callbacks share a lot of common code we
can easily factor to avoid duplication and mistakes.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The next_event logic was setting the next interval to fire in the
current timer value instead of the interval value register, which is
obviously wrong.

Plus, the logic to set the actual value was wrong as well: the interval
register can only be modified when the timer is disabled, and then
enable it back, otherwise, it'll have no effect. Fix this logic as well
since that code couldn't possibly work.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Even if in our case, this clock was non-gatable, used as a parent clock
for several IPs, it still is a good idea to enable it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Use the second timer found on the Allwinner SoCs as a clock source and
sched clock, that were both not used yet on these platforms.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The name AUTORELOAD was actually pretty bad since it doesn't make the
register reload the previous interval when it expires, but setting this
value pushes the new programmed interval to the internal timer counter.
Rename it to RELOAD instead.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The macros were not using parenthesis to escape the arguments passed to
them. It is pretty unsafe, so add those parenthesis.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The sched_clock.h include is under include/linux now.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

This removes all the drivers/clocksource and drivers/irqchip uses of
the __cpuinit macros from all C files.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Rob Herring <robherring2@gmail.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Will Deacon <will.deacon@arm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source on timer1.
Corresponding device tree documentation is also added.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>

Separate the armada 370xp local timers from the local timer API.
This will allow us to remove ARM local timer support in the near
future and makes this driver multi-architecture friendly.
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>