__spi_validate makes sure that every transfer has a valid bits_per_word
and speed_hz setting. We do not need to fallback to values from the
spi_device.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

When the spi_transfer given in spi_imx_setupxfer is NULL then
we have nothing to do. Bail out early in this case so that
we do not have to test for t != NULL multiple times later.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

This reverts commits 8d4a6cad and
179547e1.

Besides the problems already found with this patch it also modifies
the spi transfer tx_buf in spi_imx_u32_swap_u8() and spi_imx_u32_swap_u16().
This is hidden from the compiler with an explicit cast from const void*
to u32*, so no warning is issued.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

In case either transfer->tx_buf or transfer->rx_buf is NULL,
manipulation of buffer in spi_imx_u32_swap_u[8|16]() will cause
NULL pointer dereference crash.

Add buffer check at very beginning of spi_imx_u32_swap_u[8|16](),
to avoid such crash.
Signed-off-by: NJiada Wang <jiada_wang@mentor.com>
Reported-by: NLeonard Crestez <leonard.crestez@nxp.com>
Tested-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

previously burst length (BURST_LENGTH) is always set to equal
to bits_per_word, causes a 10us gap between each word in
transfer, which significantly affects performance.

This patch uses 32 bits transfer to simulate lower bits transfer,
and adjusts burst length runtimely to use biggeest burst length
as possible to reduce the gaps in transfer for PIO mode.
Signed-off-by: NJiada Wang <jiada_wang@mentor.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

This patch implements consideration of the SPI_READY mode flag as
defined in spi.h. It extends the device tree bindings to support
the values defined by the reference manual for the DRCTL field.

Thus supporting edge-triggered and level-triggered bursts.
Signed-off-by: NLeif Middelschulte <Leif.Middelschulte@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Previously DMA watermark level is configured to fifosize/2,
DMA mode can be used only when transfer length can be divided
by 'watermark level * bpw', which makes DMA mode not pratical.

This patch adjusts watermark level to largest number (no bigger
than fifosize/2) which can divide 'tranfer length / bpw' for
each transfer.
Signed-off-by: NJiada Wang <jiada_wang@mentor.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Introduce additional output parameter in spi_imx_clkdiv_1()
function to return result frequency and set it to spi_bus_clk.

This fixes division by zero bug, which occurred in
spi_imx_calculate_timeout() function.
Signed-off-by: NRobert Baldyga <r.baldyga@hackerion.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Support DMA transfers on imx35 and compatible chipsets (imx31, imx25).

If DMA can be used, set the start mode control (SMC) bit to start the
SPI burst as soon as data is written into the tx fifo. Configure DMA
requests when the fifo is half empty during tx or half full during rx.
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Signed-off-by: NMark Brown <broonie@kernel.org>

Fix to return error code -EINVAL if no CS GPIOs available
instead of 0, as done elsewhere in this function.

Fixes: f13d4e18 ("spi: imx: Gracefully handle NULL master->cs_gpios")
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

It is possible that master->cs_gpios is NULL after spi_bitbang_start(),
this happens if the master has no CS GPIOs specified in DT. Check for
this case after spi_bitbang_start() to prevent NULL pointer dereference
in the subsequent for loop, which accesses the master->cs_gpios field.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Martin Kaiser <martin@kaiser.cx>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

imx35 and compatible chipsets support loopback mode by setting a
loopback control bit in the test register. Make this setting available
for data transfers, similar to what we do for imx51.
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Signed-off-by: NMark Brown <broonie@kernel.org>

Modify spi_imx_clkdiv_2() to return the resulting bus clock frequency
when the selected clock divider is applied. Set spi_imx->spi_bus_clk to
this frequency.

If spi_bus_clk is unset, spi_imx_calculate_timeout() causes a
division by 0.
Signed-off-by: NMartin Kaiser <martin@kaiser.cx>
Signed-off-by: NMark Brown <broonie@kernel.org>

In some rare cases I see the following 'task blocked' information. It
looks like the PIO transfer has some problems and never succeeds. Make
use of wait_for_completion_timeout(..) to detect this case and
return -ETIMEDOUT.

[ 240.246067] INFO: task hexdump:1660 blocked for more than 120 seconds.
[ 240.246089] Not tainted 4.1.17 0000001
[ 240.246099] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 240.246109] hexdump D c0575548 0 1660 1 0x00000000
[ 240.246132] Backtrace:
[ 240.246166] [<c057524c>] (__schedule) from [<c0575a84>] (schedule+0x40/0xa4)
[ 240.246176] r10:00000000 r9:c07f1300 r8:c07b8408 r7:c0576518 r6:7fffffff r5:7fffffff
[ 240.246210] r4:ee972e7c
[ 240.246233] [<c0575a44>] (schedule) from [<c0578544>] (schedule_timeout+0x174/0x274)
[ 240.246254] [<c05783d0>] (schedule_timeout) from [<c0576518>] (wait_for_common+0xc0/0x164)
[ 240.246263] r10:00000000 r9:c07f1300 r8:00000002 r7:00000000 r6:7fffffff r5:ee972e78
[ 240.246294] r4:ee972e7c
[ 240.246314] [<c0576458>] (wait_for_common) from [<c05765dc>] (wait_for_completion+0x20/0x24)
[ 240.246324] r10:ee972e50 r8:00000001 r7:c3976200 r6:ee972c00 r5:ee972e50 r4:c2c87d28
[ 240.246367] [<c05765bc>] (wait_for_completion) from [<c03f6b04>] (spi_imx_transfer+0xe8/0x3cc)
[ 240.246393] [<c03f6a1c>] (spi_imx_transfer) from [<c03f50e4>] (spi_bitbang_transfer_one+0xb4/0x250)
[ 240.246403] r10:ee972e50 r8:00000001 r7:00000000 r6:c2c87da0 r5:00000000 r4:c2c87d28
[ 240.246443] [<c03f5030>] (spi_bitbang_transfer_one) from [<c03f36e8>] (__spi_pump_messages+0x36c/0x6b4)
[ 240.246452] r10:ee9e5010 r9:00000001 r8:ee9e5010 r7:00000000 r6:c2c87da0 r5:c2c87d6c
[ 240.246483] r4:ee972c00
[ 240.246503] [<c03f337c>] (__spi_pump_messages) from [<c03f3b68>] (__spi_sync+0x138/0x1e4)
[ 240.246512] r10:00000000 r9:00000000 r8:c03f25a8 r7:00000000 r6:ee972c00 r5:c3976200
[ 240.246542] r4:c2c87da0
[ 240.246562] [<c03f3a30>] (__spi_sync) from [<c03f3c50>] (spi_sync+0x1c/0x20)
[ 240.246571] r10:00040000 r9:00000000 r8:c3976200 r7:00000000 r6:ee973300 r5:c2c87da0
[ 240.246602] r4:ee973014
[ 240.246623] [<c03f3c34>] (spi_sync) from [<c03f0210>] (m25p80_read+0xf8/0x124)
[ 240.246641] [<c03f0118>] (m25p80_read) from [<c03f1528>] (spi_nor_read+0x64/0x80)
[ 240.246651] r10:00004000 r8:00004000 r7:00000000 r6:00040000 r5:00000000 r4:ee973014
[ 240.246698] [<c03f14c4>] (spi_nor_read) from [<c03cdcb4>] (mtd_read+0x98/0xcc)
[ 240.246708] r7:c2c87ea0 r6:ee973098 r5:00000000 r4:001c0000
[ 240.246740] [<c03cdc1c>] (mtd_read) from [<c03d300c>] (mtdchar_read+0xcc/0x204)
[ 240.246750] r9:ed424000 r8:00000000 r7:b495d018 r6:c2c87f78 r5:00000000 r4:00040000
[ 240.246793] [<c03d2f40>] (mtdchar_read) from [<c013b1c4>] (__vfs_read+0x3c/0xe0)
[ 240.246803] r10:00004000 r9:00000000 r8:c2c87f78 r7:b495d018 r6:c2c87f78 r5:c05c8104
[ 240.246833] r4:c32fe600
[ 240.246852] [<c013b188>] (__vfs_read) from [<c013befc>] (vfs_read+0x98/0x154)
[ 240.246861] r10:00000000 r8:00040000 r7:00004000 r6:c2c87f78 r5:b495d018 r4:c32fe600
[ 240.246899] [<c013be64>] (vfs_read) from [<c013c008>] (SyS_read+0x50/0x90)
[ 240.246908] r10:00000000 r8:00040000 r7:b495d018 r6:00004000 r5:c32fe601 r4:c32fe600
[ 240.246953] [<c013bfb8>] (SyS_read) from [<c000fa60>] (ret_fast_syscall+0x0/0x3c)
[ 240.246962] r9:c2c86000 r8:c000fc04 r7:00000003 r6:00004000 r5:00000000 r4:b495d018
Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The SPI-driver no longer contains the conditions for various CPUs, so
"maybe_unused" attributes is no longer needed.
This patch removes these attributes.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NMark Brown <broonie@kernel.org>

SPI mode can be obtained directly from spi-device, there is no
need to keep a copy.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NMark Brown <broonie@kernel.org>

Patch reuse existing "chip_select" and "cs_gpio(s)" fields from SPI core.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NMark Brown <broonie@kernel.org>

transfer could be NULL in spi_imx_can_dma() when it's called from
spi_imx_setupxfer() with a NULL transfer. Test for a NULL pointer before
dereferencing it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

If the SPI chip select (CS) for a dedicated channel is done manually by
the used higher device driver, the CS may be active while writing to
ECSPIx_CONFIGREG. To prevent unwanted clock edges when selecting
the clock mode,  only do the necessary changes to the i.MX SPI
configuration register and leave not selected channels untouched.

To prevent unwanted clock edges on first use, an empty dummy
transmission shall be done by the initialization procedure of the device
driver of this channel. This will set the clock mode to the correct state.
Signed-off-by: NKnut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

The driver tries to be clever by only setting up DMA channels when
the corresponding sg tables are non NULL. The sg tables are embedded
structs in struct spi_transfer, so they are guaranteed to be non NULL
which makes the if(tx)/if(rx) tests completely bogus. The driver even
sets the SPI_MASTER_MUST_RX / SPI_MASTER_MUST_TX flags which makes sure
the sg tables are not only present but also non empty.
Drop the tests and make the DMA path easier to follow.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

Now that the config function knows whether we are doing DMA or not we
can do the necessary register setup in the config function and no longer
have to do this in the trigger function. With this the trigger function
becomes a no-op for DMA, so instead of testing if we are doing DMA or
not in the trigger function we simply no longer call it in the DMA case.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

The watermark levels in the DMA register are write only, the driver
should never have to read them back from the hardware. Replace the
current _MASK and _OFFSET defines with defines taking the watermark
level directly.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

This reverts patch 1476253c (spi: imx: fix ecspi mode setup)
The patch tried to fix something by clearing bits in the cfg variable,
but cfg is initialized to zero on function entry. There are no bits to
clear.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

DMA transfer for SPI was limited to up to 8 bits word size until now.
Sync in SPI burst size and DMA bus width is necessary to correctly
support 16 and 32 BPW.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

There's no need for an extra dma_is_inited variable when we can
equally well check for the existence of a DMA channel.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

When the MX51_ECSPI_DMA is configured we control every single bit
of the register, so there's no need to read/modify/write it. Instead
just write the value we want to have in the register. Also, drop
unnecessary check if we are actually doing DMA. The values written
to the register have no effect in PIO mode and value written there
during the last DMA transfer is still in the register, so we can
equally well always write a value.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

The SoC specific config function does not know if DMA will be used or
not. This information will be useful to configure the SPI controller
correctly for DMA in following patches, so initialize the usedma
variable before calling into the SoC specific config function.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

At the moment the driver decides to fallback to PIO mode the buffers
are already mapped for DMA. It's a bug to access them with the CPU
afterwards, so we cannot just fallback to PIO mode.
It should not be necessary anyway, since we only use DMA when we
verified that it's possible in the fist place, so when prep_slave_sg
fails it's a bug, either in the SDMA driver or in the can_dma
implementation.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

Fixed timeout value can fire while transaction is ongoing. This may happen
because there are no strict requirements on SPI transaction duration.
Dynamic timeout value is generated based on SCLK and transaction size.

There is also 4 * SCLK delay between TX bursts related to HW internal CS change.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

In spi_imx_dma_transfer(), when desc_rx = dmaengine_prep_slave_sg()
fails, the context goes to label no_dma and then return. However,
the memory allocated for desc_tx has not been freed yet, which leads
to resource leak.
Signed-off-by: NGao Pan <pandy.gao@nxp.com>
Reviewed-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add a struct device * member to the private driver data and use
it to print messages using dev_* functions rather than pr_*.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

RX DMA tail data handling doesn't work correctly in many cases with current
implementation. It happens because SPI core was setup to generates both RX
and RX TAIL events. And RX TAIL event does not work correctly.
This can be easily verified by sending SPI transaction with size modulus
WML(32 in our case) not equal 0.

Also removing change introduced in f6ee9b58
since this change only fix usecases with transfer size from 33 to 128 bytes
and doesn't fix 129 bytes and bigger.

This is output from transaction with len 138 bytes in loopback mode at 10Mhz:
TX0000: a3 97 a2 55 53 be f1 fc f9 79 6b 52 14 13 e9 e2
TX0010: 2d 51 8e 1f 56 08 57 27 a7 05 d4 d0 52 82 77 75
TX0020: 1b 99 4a ed 58 3d 6a 52 36 d5 24 4a 68 8e ad 95
TX0030: 5f 3c 35 b5 c4 8c dd 6c 11 32 3d e2 b4 b4 59 cf
TX0040: ce 23 3d 27 df a7 f9 96 fc 1e e0 66 2c 0e 7b 8c
TX0050: ca 30 42 8f bc 9f 7b ce d1 b8 b1 87 ec 8a d6 bb
TX0060: 2e 15 63 0e 3c dc a4 3a 7a 06 20 a7 93 1b 34 dd
TX0070: 4c f5 ec 88 96 68 d6 68 a0 09 6f 8e 93 47 c9 41
TX0080: db ac cf 97 89 f3 51 05 79 71

RX0000: a3 97 a2 55 53 be f1 fc f9 79 6b 52 14 13 e9 e2
RX0010: 2d 51 8e 1f 56 08 57 27 a7 05 d4 d0 52 82 77 75
RX0020: 1b 99 4a ed 58 3d 6a 52 36 d5 24 4a 68 8e ad 95
RX0030: 5f 3c 35 00 00 b5 00 00 00 c4 00 00 8c 00 00 dd
RX0040: 6c 11 32 3d e2 b4 b4 59 cf ce 23 3d 27 df a7 f9
RX0050: 96 fc 1e e0 66 2c 0e 7b 8c ca 30 42 8f 1f 1f bc
RX0060: 9f 7b ce d1 b8 b1 87 ec 8a d6 bb 2e 15 63 0e ed
RX0070: ed 3c 58 58 58 dc 3d 3d a4 6a 6a 3a 52 52 7a 36
RX0080: 06 20 a7 93 1b 34 dd 4c f5 ec

Zeros at offset 33 and 34 caused by reading empty RX FIFO which not possible
if DMA RX read was triggered by RX event. This mean DMA was triggered
by RX TAIL event.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>

In spi_imx_dma_transfer(), when desc_rx = dmaengine_prep_slave_sg()
fails, the context goes to label no_dma and then return. However,
the memory allocated for desc_tx has not been freed yet, which leads
to resource leak.
Signed-off-by: NGao Pan <pandy.gao@nxp.com>
Reviewed-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

If SPI device supports DMA mode, but DMA controller is not yet
available due to e.g. a delay in the corresponding kernel module
initialization, retry to initialize SPI driver later on instead of
falling back into PIO only mode.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

On SDMA initialization return exactly the same error, which is
reported by dma_request_slave_channel_reason(), it is a preceding
change to defer SPI DMA initialization, if SDMA module is not yet
available.
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Limit SPI_LOOP mode to ECSPI controller (iMX.51, iMX53 and i.MX6) only since
there is no support in other families specific code for now.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

If controller hold in reset it's not possible to write any
register except CTRL. So all other registers must be updated
only after controller bring out from reset.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Similar to other controller type checks add check function for
IMX51. It includes IMX53 and IMX6.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

There is no need to have different watermarks levels since they are the same.
Merge them into one WML parameter.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

The overflow may happen due to rescheduling for another task and/or interrupt
if we enable SPI HW before starting RX DMA. So RX DMA enabled first to make
sure data would be read out from FIFO ASAP. TX DMA enabled next to start
filling TX FIFO with new data. And finaly SPI HW enabled to start actual
data transfer.

The risk rise in case of heavy system load and high SPI clock.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>