The overflow may happen due to rescheduling for another task and/or interrupt
if we enable SPI HW before starting RX DMA. So RX DMA enabled first to make
sure data would be read out from FIFO ASAP. TX DMA enabled next to start
filling TX FIFO with new data. And finaly SPI HW enabled to start actual
data transfer.

The risk rise in case of heavy system load and high SPI clock.
Signed-off-by: NAnton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>