Add support for the graphics clock controller found on SDM845
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: NAmit Nischal <anischal@codeaurora.org>
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Collapse return in probe into less lines]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Tested-by: NCraig Tatlor <ctatlor97@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Tested-by: NCraig Tatlor <ctatlor97@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Tested-by: NCraig Tatlor <ctatlor97@gmail.com>
[sboyd@kernel.org: Move hidden config to top outside of the visible qcom
config zone so that menuconfig looks nice]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Tested-by: NCraig Tatlor <ctatlor97@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: NShefali Jain <shefjain@codeaurora.org>
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Co-developed-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NAnu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: NCraig Tatlor <ctatlor97@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the camera clock controller found on SDM845
based devices. This would allow camera drivers to probe and
control their clocks.
Signed-off-by: NAmit Nischal <anischal@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Clean up whitespace, indentation, remove
cmd_db_ready check]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the video clock controller found on SDM845
based devices. This would allow video drivers to probe and
control their clocks.
Signed-off-by: NAmit Nischal <anischal@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the global clock controller found on SDM845
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NAmit Nischal <anischal@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the global clock controller found on MSM8998
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: NJoonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: NImran Khan <kimran@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
[bjorn: Specify regs for alpha_plls, fix white spaces and add binding]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add a driver for the APCS clock controller. It is part of the APCS
hardware block, which among other things implements also a combined
mux and half integer divider functionality. It can choose between a
fixed-rate clock or the dedicated APCS (A53) PLL. The source and the
divider can be set both at the same time.

This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NAmit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Include rcg header for parent_map, drop
multiple unneeded includes, add COMPILE_TEST to APCS depends,
made tristate/modular]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.

This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NAmit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Clkdiv module provides a clock output on the PMIC with CXO as
the source. This clock can be routed through PMIC GPIOs. Add
a device driver to configure this clkdiv module.
Signed-off-by: NTirupathi Reddy <tirupath@codeaurora.org>
[sboyd: Simplified code and moved to devm clk provider APIs]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on
the ipq8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.

The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.cSigned-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove useless braces for single line if]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock definition was ported from the Google 3.10 kernel tree to
work with the latest kernel.
Signed-off-by: NBastian Köcher <mail@kchr.de>
[jeremymc@redhat.com: created new commit of just dt-bindings]
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
[sboyd@codeaurora.org: Tidy up commit text and Kconfig help]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock
controllers, as these provide some of the gdscs on the SOC.

Also selecting this config will make it align with other drivers which
do the same.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 52111672 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC")
Fixes: 7e824d50 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In order to support the Qualcomm MDM9615 SoC, add support for
the Global and LPASS Clock Controllers.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NPradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: NSenthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NMatthew McClintock <mmcclint@codeaurora.org>
Acked-by: NAndy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Having this hidden config below the COMMON_CLK_QCOM config causes
menuconfig to stop indenting config items after it.

        <*> Support for Qualcomm's clock controllers
        {M}   APQ8084 Global Clock Controller
        <M>   APQ8084 Multimedia Clock Controller
        {M}   IPQ806x Global Clock Controller
        <M>   IPQ806x LPASS Clock Controller
        <M> MSM8660 Global Clock Controller
        <M> MSM8916 Global Clock Controller
        {M} APQ8064/MSM8960 Global Clock Controller
        <M> APQ8064/MSM8960 LPASS Clock Controller
        <M> MSM8960 Multimedia Clock Controller
        {M} MSM8974 Global Clock Controller
        <M> MSM8974 Multimedia Clock Controller

Move it up above anything else so that we don't get odd
indenting.

Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: NStephane Viau <sviau@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There's just one GDSC as part of the msm8974 GCC block.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Support for Qualcomm's clock controllers should be available only
on Qualcomm platforms.
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe and control
their clocks and resets.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
[sboyd@codeaurora.org: Removed NULL entry from parent_maps]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add an LCC driver for MSM8960/APQ8064 that supports the i2s,
slimbus, and pcm clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NJosh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.

This is currently missing clocks for USB HSIC and networking devices.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on
the APQ8084 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The APQ8064 and MSM8960 share a significant amount of clock data and
code between the two SoCs.  Rather than duplicating the data we just add
support for a unqiue APQ8064 clock table into the MSM8960 code.

For now add just enough clocks to get a basic serial port going on an
APQ8064 device.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: trivial conflict due to missing ipq8064 support]