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  1. 28 11月, 2018 1 次提交
  3. 19 10月, 2018 2 次提交
  5. 18 10月, 2018 8 次提交
  7. 17 10月, 2018 3 次提交
  9. 31 8月, 2018 3 次提交
  11. 29 8月, 2018 2 次提交
  13. 28 8月, 2018 2 次提交
    • T
      clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 · 8b69c6db
      由 Taniya Das 提交于 
      QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Use new macro, split out init structures so they
don't have to be copied]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      8b69c6db
    • T
      clk: qcom: Add support for RCG to register for DFS · cc4f6944
      由 Taniya Das 提交于 
      Dynamic Frequency switch is a feature of clock controller by which request
from peripherals allows automatic switching frequency of input clock
without SW intervention. There are various performance levels associated
with a root clock. When the input performance state changes, the source
clocks and division ratios of the new performance state are loaded on to
RCG via HW and the RCG switches to new clock frequency when the RCG is in
DFS HW enabled mode.

Register the root clock generators(RCG) to switch to use the dfs clock ops
in the cases where DFS is enabled. The clk_round_rate() called by the clock
consumer would invoke the dfs determine clock ops and would read the DFS
performance level registers to identify all the frequencies supported and
update the frequency table. The DFS clock consumers would maintain these
frequency mapping and request the desired performance levels.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Rework registration logic to stop copying, change
recalc_rate() to index directly into the table if possible and fallback
to calculating on the fly with an assumed correct parent]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      cc4f6944
  15. 01 8月, 2018 1 次提交
  17. 26 7月, 2018 1 次提交
  19. 17 7月, 2018 1 次提交
  21. 07 7月, 2018 3 次提交
    • T
      clk: qcom: Move frequency table macro to common file · da172d2b
      由 Taniya Das 提交于 
      Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      da172d2b
    • V
      clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ON · 53f3abe9
      由 Vivek Gautam 提交于 
      Patch (7705bb71 clk: qcom: mmcc-msm8996: leave all mmagic gdscs
and clocks always enabled") makes all mmgaic gdscs ALWAYS_ON.
The mmagic_bimc_gdsc is also needed to be turned on to get display
working on 8x96.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 7705bb71 ("clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      53f3abe9
    • V
      clk: qcom: gcc-msm8996: Disable halt check on UFS tx clock · 5f75b78d
      由 Vinod Koul 提交于 
      Commit 12d807cd ("clk: qcom: gcc-msm8996: Disable halt check on UFS
clocks") marked BRANCH_HALT_SKIP for ufs rx clocks, but missed ufs tx
clocks. The result of that is kernel warnings at reboot:

[  105.624283] gcc_ufs_tx_symbol_0_clk status stuck at 'on'
[  105.624311] WARNING: CPU: 1 PID: 1 at drivers/clk/qcom/clk-branch.c:100 clk_branch_toggle+0x190/0x1b0
[  105.633235] Modules linked in:
[  105.645118] CPU: 1 PID: 1 Comm: systemd-shutdow Tainted: G        W         4.18.0-rc2-00002-g2bfbe52a53a3 #11
[  105.647988] Hardware name: Qualcomm Technologies, Inc. DB820c (DT)
[  105.657966] pstate: 60000085 (nZCv daIf -PAN -UAO)
[  105.664127] pc : clk_branch_toggle+0x190/0x1b0
[  105.668900] lr : clk_branch_toggle+0x190/0x1b0
[  105.673324] sp : ffff00000805bb40
[  105.677751] x29: ffff00000805bb40 x28: 0000000000000000
[  105.681140] x27: ffff8000d947cc60 x26: 0000000000000001
[  105.686520] x25: ffff000008f71900 x24: 0000000000000000
[  105.691816] x23: ffff00000925e338 x22: ffff00000855f8e0
[  105.697114] x21: 0000000000000000 x20: 0000000000000000
[  105.702407] x19: ffff0000091c9000 x18: ffffffffffffffff
[  105.707702] x17: 0000ffffac148c58 x16: ffff000008b82928
[  105.712998] x15: ffff0000091c96c8 x14: ffff0000893817c7
[  105.718293] x13: ffff0000093817d5 x12: ffff0000091c9940
[  105.723587] x11: ffff0000085e3e70 x10: ffff00000805b780
[  105.728884] x9 : ffff00000805bb40 x8 : 7320737574617473
[  105.734179] x7 : 206b6c635f305f6c x6 : 00000000000001e5
[  105.739472] x5 : 0000000000000000 x4 : 0000000000000000
[  105.744769] x3 : ffffffffffffffff x2 : ffff0000091e2658
[  105.750063] x1 : a7c4712dd5e09c00 x0 : 0000000000000000
[  105.755360] Call trace:
[  105.760652]  clk_branch_toggle+0x190/0x1b0
[  105.762824]  clk_branch2_disable+0x18/0x20
[  105.766994]  clk_core_disable+0x58/0xa8
[  105.771069]  clk_core_disable_lock+0x20/0x38
[  105.774803]  clk_disable+0x1c/0x28
[  105.779320]  __ufshcd_setup_clocks+0x298/0x308
[  105.782529]  ufshcd_suspend+0x160/0x308
[  105.786953]  ufshcd_shutdown+0x38/0xa0
[  105.790690]  ufshcd_pltfrm_shutdown+0x10/0x18
[  105.794512]  platform_drv_shutdown+0x20/0x30
[  105.798935]  device_shutdown+0x110/0x1e8
[  105.803278]  kernel_restart_prepare+0x34/0x40
[  105.807181]  kernel_restart+0x14/0x78
[  105.811434]  sys_reboot+0x200/0x248
[  105.815081]  el0_svc_naked+0x30/0x34
[  105.818378] ---[ end trace 8d2322276b27879c ]---

Mark gcc_ufs_tx_symbol_0_clk as BRANCH_HALT_SKIP as well.

Fixes: 12d807cd ("clk: qcom: gcc-msm8996: Disable halt check on UFS clocks")
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      5f75b78d
  23. 04 7月, 2018 1 次提交
  25. 20 6月, 2018 1 次提交
    • J
      clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks · 04cdd5af
      由 Jerome Brunet 提交于 
      the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:
* clk_prepare_enable()
* clk_set_rate()

on SDCx_clk which is a children of SDCx_src. SDCx_src has
CLK_SET_RATE_GATE so this sequence should not be allowed but this was not
enforced. IOW, the flag is ignored. Dropping the flag won't change
anything to the current behaviour of the platform.

CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept,
the mmci driver would receive -EBUSY when calling clk_set_rate()
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com
      04cdd5af
  27. 07 6月, 2018 1 次提交
    • K
      treewide: Use struct_size() for devm_kmalloc() and friends · 0ed2dd03
      由 Kees Cook 提交于 
      Replaces open-coded struct size calculations with struct_size() for
devm_*, f2fs_*, and sock_* allocations. Automatically generated (and
manually adjusted) from the following Coccinelle script:

// Direct reference to struct field.
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@

- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

// mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@

- alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
+ alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP)

// Same pattern, but can't trivially locate the trailing element name,
// or variable name.
@@
identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc";
expression HANDLE;
expression GFP;
expression SOMETHING, COUNT, ELEMENT;
@@

- alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
+ alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)
Signed-off-by: NKees Cook <keescook@chromium.org>
      0ed2dd03
  29. 02 6月, 2018 7 次提交
  31. 11 5月, 2018 1 次提交
    • E
      clk: qcom: Base rcg parent rate off plan frequency · c7d2a0eb
      由 Evan Green 提交于 
      _freq_tbl_determine_rate uses the pre_div found in the clock plan
multiplied by the requested rate from the caller to determine the
best parent rate to set. If the requested rate is not exactly equal
to the rate that was found in the clock plan, then using the requested
rate in parent rate calculations is incorrect. For instance, if 150MHz
was requested, but 200MHz was the match found, and that plan had a
pre_div of 3, then the parent should be set to 600MHz, not 450MHz.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Fixes: bcd61c0f ("clk: qcom: Add support for root clock generators (RCGs)")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
      c7d2a0eb
  33. 09 5月, 2018 2 次提交