1. 30 7月, 2015 2 次提交
  2. 29 7月, 2015 6 次提交
  3. 27 7月, 2015 5 次提交
    • F
      irqchip/bcm7120-l2: Fix interrupt status for multiple parent IRQs · 0aef3997
      Florian Fainelli 提交于
      Our irq-bcm7120-l2 interrupt controller driver utilizes the same handler
      function for the different parent interrupts it services: UPG_MAIN, UPG_BSC for
      instance.
      
      The problem is that function reads the IRQSTAT register which can combine
      interrupt causes for different parent interrupts, such that we can end-up in
      the following situation:
      
      - CPU takes an interrupt
      - bcm7120_l2_intc_irq_handle() reads IRQSTAT
      - generic_handle_irq() is invoked
      - there are still pending interrupts flagged in IRQSTAT from a different parent
      - handle_bad_irq() is invoked for these since they come from a different irq_desc/irq
      
      In order to fix this, make sure that we always mask IRQSTAT with the
      appropriate bits that correspond go the parent interrupt source this is coming
      from. To simplify things, associate an unique structure per parent interrupt
      handler to avoid multiplying the number of lookups.
      
      Fixes: a5042de2 ("irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller")
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: cernekee@gmail.com
      Cc: jason@lakedaemon.net
      Cc: bcm-kernel-feedback-list@broadcom.com
      Cc: gregory.0xf0@gmail.com
      Cc: computersforpeace@gmail.com
      Link: http://lkml.kernel.org/r/1437691941-3100-1-git-send-email-f.fainelli@gmail.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      0aef3997
    • B
      irqchip/bcm7120-l2: Perform suspend/resume even without installed child IRQs · fd537766
      Brian Norris 提交于
      Make use of the new irq_chip_generic suspend/resume callbacks.
      
      This is required because if there are no installed child IRQs for this
      chip, the irq_chip::irq_{suspend,resume} functions will not be called.
      However, we still need to save/restore the forwarding mask, to enable
      the top-level GIC interrupt; otherwise, we lose UART output after S3
      resume.
      
      In addition to refactoring the callbacks, we have to self-initialize the
      mask cache, since the genirq core also doesn't initialize this until the
      first child IRQ is installed.
      
      The original problem report is described in extra detail here:
      http://lkml.kernel.org/g/20150619224123.GL4917@ld-irv-0074Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Cc: Gregory Fong <gregory.0xf0@gmail.com>
      Cc: bcm-kernel-feedback-list@broadcom.com
      Cc: linux-mips@linux-mips.org
      Cc: Kevin Cernekee <cernekee@chromium.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1437607300-40858-2-git-send-email-computersforpeace@gmail.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      fd537766
    • N
      irqchip: Appropriate __init annotation for const data · c376023b
      Nicolas Pitre 提交于
      Init data marked const should be annotated with __initconst for
      correctness and not __initdata.  And for those already __initconst,
      they should be qualified as const at the compiler level too.
      This also fixes LTO builds that otherwise fail with section mismatch
      errors.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/alpine.LFD.2.20.1507241511551.1806@knanqh.ubzrSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      c376023b
    • S
      irqchip/gic: Remove redundant gic_set_irqchip_flags · 0d3f2c92
      Sudeep Holla 提交于
      Now that the GIC chip implementation enables IRQCHIP_SKIP_SET_WAKE and
      IRQCHIP_MASK_ON_SUSPEND by default, the platforms requiring them need
      not override the irqchip flags as before.
      
      This patch removes all the users of gic_set_irqchip_flags and the
      function itself.
      Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Simon Horman <horms@verge.net.au>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Link: http://lkml.kernel.org/r/1436971109-20189-2-git-send-email-sudeep.holla@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      0d3f2c92
    • S
      irqchip/gic: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND · aec89ef7
      Sudeep Holla 提交于
      The GIC controller doesn't provides any facility to configure the wakeup
      sources. For the same reason, GIC chip implementation can't provide
      irq_set_wake functionality, but that results in the irqchip core
      preventing the systems from entering sleep states like "suspend to RAM".
      
      The GICv1/v2 controllers support wakeup events. They signal these wakeup
      events even when CPU interface is disabled which means the wakeup
      outputs are always enabled with the required logic in always-on domain.
      An implementation can powerdown the GIC completely, but then the wake-up
      must be relayed to some control logic within the power controller that
      acts as wake-up interrupt controller.
      
      Setting the IRQCHIP_SKIP_SET_WAKE flags will ensure that the interrupts
      from GIC can work as wakeup interrupts and resume from suspend-to-{idle,
      ram}. The wakeup interrupt sources need to use enable_irq_wake() and the
      irqchip core will then set the IRQD_WAKEUP_STATE flag.
      
      Also it's always safer to mask all the non wakeup interrupts are masked
      at the chip level when suspending. The irqchip infrastructure can handle
      masking of those interrupts at the chip level. The chip implementation
      just have to indicate that with IRQCHIP_MASK_ON_SUSPEND.
      
      This patch enables IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND so
      that the irqchip core allows and handles the power managemant wake up
      modes.
      Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Simon Horman <horms@verge.net.au>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Link: http://lkml.kernel.org/r/1436971109-20189-1-git-send-email-sudeep.holla@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      aec89ef7
  4. 26 7月, 2015 2 次提交
  5. 25 7月, 2015 2 次提交
  6. 24 7月, 2015 23 次提交
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