SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

0-DAY kernel build testing backend reports the following.

 scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
 # many are suggestions rather than must-fix

 ERROR: Use of const init definition must use __initconst
 #80: arch/arm/mach-imx/mach-imx50.c:26:
 +static const char *imx50_dt_board_compat[] __initdata = {

While at it, fix the error globally for IMX platform.
Reported-by: NFengguang Wu <fengguang.wu@intel.com>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.

In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.

This patch fixes this issue.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Enable STMPE touchscreen support as this is used on M53EVK.
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The macro name IMX6SL_CLK_CLK_END is a little insane.  Rename it to
IMX6SL_CLK_END.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.

While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Booting a mx6q wandboard with 2GB of RAM we see the following on boot:

Booting Linux on physical CPU 0x0
Linux version 3.12.0-next-20131112+ (fabio@fabio-Latitude-E6410) (gcc version 43
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: Wandboard i.MX6 Quad Board
Truncating RAM at 10000000-8fffffff to -7f7fffff (vmalloc region overlap)
...

Select CONFIG_HIGHMEM to avoid the vmalloc region overlap.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NJingchang Lu <b35083@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Remove duplicated include.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add machine support code for the Freescale IMX50 SoC.

The IMX50 is quite similar to the Freescale IMX53, and contains many of the
same periperhal hardware modules, at the same address offsets as the IMX53.
(Notable exceptions are that the IMX50 contains no CAN bus hardware, less
GPIO, no VPU, it does contain an Electrophoretic display controller though).

This support code uses some of the IMX53 setup code to reduce duplication
of what would be identical init IO setup.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The code for irq priorisation support doesn't have any in-tree users and
the Kconfig description does wrong promises because nowadays irq
handlers are called with irqs disabled, so no high prioritized irq can
interrupt a lower prioritized handler.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Today, imx53 handles iomux configuration using pinctrl driver, so
mxc_iomux_v3_init() call in imx53_init_early() is there for nothing.
Remove the call from there.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The eukrea cpuimx35 and cpuimx51 have a tsc2007 touchscreen controller,
  so we turn it on.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: linux-input@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Lothar Waßmann <LW@KARO-electronics.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Allow the Freescale IMX50 SoC support code to be configured on.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add code to support the specific clock tree of the Freescale IMX50 SoC.
It can use much of the common IMX51/IMX53 clocking code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add appropriate UART address definitions and support defines for using the
UARTs of the Freescale IMX50 SoC as debug ports.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The eukrea mbimxsd25 has a gpio regulator for enabling its
  LCD display, it also has a gpio button.

We enable the respective drivers in order to be able to use theses
  features with this configuration.

Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The PEX860X has GPIO's which are used for PCI Reset lines on the
Gateworks Ventana boards.  The GPIO's need to be set as output
level high so as to allow the PCIe devices to come out of reset.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Some of the clocks that were designated gate-clk do not have a gate, so
change those clocks to be of periph-clk type.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Update Kconfig to enable TWD.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Enable MMC/SD on the Broadcom mobile platforms, and increase the block
minors from the default 8 to 16 (since the Broadcom board by default
has root on the 8th partition).
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: stable@vger.kernel.org # v3.12

This enables a few more options on the sunxi defconfigs such that I can
use nfsroot to boot them (there is no local storage support yet). It
also enables PRINTK_TIME and tmpfs since it's a common distro requirement.
Signed-off-by: NOlof Johansson <olof@lixom.net>

BeagleBone Black uses the TI CPSW ethernet controller, enable it in the
multi_v7_defconfig for testing coverage purposes.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: stable@vger.kernel.org # v3.12

drivers/net/ethernet/smsc/smsc911x.c is expecting supplies named
"vdd33a" and "vddvario". Currently the shared DTS file provides
"vmmc" and "vmmc_aux", and the supply lookup will fail:

smsc911x 2c000000.ethernet: Looking up vdd33a-supply from device tree
smsc911x 2c000000.ethernet: Looking up vdd33a-supply property in node /ocp/gpmc@6e000000/ethernet@gpmc failed
smsc911x 2c000000.ethernet: Looking up vddvario-supply from device tree
smsc911x 2c000000.ethernet: Looking up vddvario-supply property in node /ocp/gpmc@6e000000/ethernet@gpmc failed

Fix it!

Looks like commmit 6b2978ac (ARM: dts: Shared file for omap GPMC
connected smsc911x) made the problem more visible by moving the smc911x
configuration from the omap3-igep0020.dts file to the generic file.
But it seems we've had this problem since commit d72b4415
(ARM: dts: omap3-igep0020: Add SMSC911x LAN chip support).

Tested on OMAP3 Overo platform.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
[tony@atomide.com: updated comments for the commits causing the problem]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit 'cd8abed1' "ARM: OMAP2+: Powerdomain: Remove the need to
always have a voltdm associated to a pwrdm" leads to the following
Smatch complaint:

arch/arm/mach-omap2/powerdomain.c:131 _pwrdm_register()
	 error: we previously assumed 'arch_pwrdm' could be null (see line 105)

So, fix the unchecked dereference of arch_pwrdm.
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This adds typical McBSP2-TWL4030 audio description to the legacy
Beagle Board.
Signed-off-by: NJarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Mux mode for wlan/sdmmc5 should be MODE0 in pinmux_wl12xx_pins and
Enable Pull up on sdmmc5_clk to detect SDIO card.

This fixes WLAN on omap4-sdp that got broken in v3.10 when we
moved omap4 to boot using device tree only as I did not have
the WL12XX card in my omap4 SDP to test with. The commit that
attempted to make WL12XX working on omap4 SDP was 775d2418
(ARM: dts: Fix muxing and regulator for wl12xx on the SDIO
bus for blaze).
Signed-off-by: NBalaji T K <balajitk@ti.com>
[tony@atomide.com: updated comments for the regression]
Signed-off-by: NTony Lindgren <tony@atomide.com>

pin mux wl12xx_gpio and wl12xx_pins should be part of omap4_pmx_core
and not omap4_pmx_wkup. So, move wl12xx_* to omap4_pmx_core.

Fix the following error message:
pinctrl-single 4a31e040.pinmux: mux offset out of range: 0x38 (0x38)
pinctrl-single 4a31e040.pinmux: could not add functions for pinmux_wl12xx_pins 56x

SDIO card is not detected after moving pin mux to omap4_pmx_core since
sdmmc5_clk pull is disabled. Enable Pull up on sdmmc5_clk to detect SDIO card.

This fixes a regression where WLAN did not work after a warm reset
or after one up/down cycle that happened when we move omap4 to boot
using device tree only. For reference, the kernel bug is described at:

https://bugzilla.kernel.org/show_bug.cgi?id=63821

Cc: stable@vger.kernel.org # v3.10+
Signed-off-by: NBalaji T K <balajitk@ti.com>
[tony@atomide.com: update comments to describe the regression]
Signed-off-by: NTony Lindgren <tony@atomide.com>

If CONFIG_PM is not defined, then arch/arm/mach-at91/pm.c is not
compiled in.  This patch creates an inline function that does nothing
if CONFIG_PM is not defined.
Signed-off-by: NBrent Taylor <motobud@gmail.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Alias was missing for SoC of the at91sam9x5 familly that embed USART3.
Reported-by: NJiri Prchal <jiri.prchal@aksignal.cz>
[b.brezillon@overkiz.com: advised to place changes in at91sam9x5_usart3.dtsi]
Acked-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

With some devices, transfer hangs during I2C frame transmission. This issue
disappears when reducing the internal frequency of the TWI IP. Even if it is
indicated that internal clock max frequency is 66MHz, it seems we have
oversampling on I2C signals making TWI believe that a transfer in progress
is done.

This fix has no impact on the I2C bus frequency.

Cc: <stable@vger.kernel.org> #3.10+
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>