“41837ca962ecb4ae7d98b00f94a51e737c8384ea”上不存在“README.md”
- 11 4月, 2019 1 次提交
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由 Peng Ma 提交于
Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the address. Signed-off-by: NPeng Ma <peng.ma@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 20 3月, 2019 1 次提交
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由 Alison Wang 提交于
This patch adds pmu dt nodes for LS1028A. Signed-off-by: NAlison Wang <alison.wang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 19 3月, 2019 1 次提交
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由 Alison Wang 提交于
This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards. Signed-off-by: NAlison Wang <alison.wang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 02 3月, 2019 1 次提交
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由 Claudiu Manoil 提交于
The LS1028A SoC features a PCI Integrated Endpoint Root Complex (IERC) defining several integrated PCI devices, including the ENETC ethernet controller integrated endpoints (IEPs). The IERC implements ECAM (Enhanced Configuration Access Mechanism) to provide access to the PCIe config space of the IEPs. This means the the IEPs (including ENETC) do not support the standard PCIe BARs, instead the Enhanced Allocation (EA) capability structures in the ECAM space are used to fix the base addresses in the system, and the PCI subsystem uses these structures for device enumeration and discovery. The "ranges" entries contain basic information from these EA capabily structures required by the kernel for device enumeration. The current patch also enables the first 2 ENETC PFs (Physiscal Functions) and the associated VFs (Virtual Functions), 2 VFs for each PF. Each of these ENETC PFs has an external ethernet port on the LS1028A SoC. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 08 12月, 2018 1 次提交
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由 Bhaskar Upadhaya 提交于
LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache Features summary Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs - Arranged as single clusters of two cores sharing a 1 MB L2 cache - Speed Up to 1.3 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 400 MHz 32-bit DDR4 SDRAM memory controller with ECC Two PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Two high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1028A SoC family: - fsl-ls1028a.dtsi: DTS-Include file for NXP LS1028A SoC. - fsl-ls1028a-qds.dts: DTS file for NXP LS1028A QDS board. - fsl-ls1028a-rdb.dts: DTS file for NXP LS1028A RDB board Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: NRai Harninder <harninder.rai@nxp.com> Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: NLi Yang <leoyang.li@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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