In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power
domain. This is similar to the other hardware modules and their power
domains. However there is one thing specific to G3D clocks hierarchy.
Unlike other hardware modules, the G3D clocks hierarchy doesn't have any
gate clock between the TOP part of the hierarchy and the part located in
the power domain and some SoC internal busses are sourced directly from
the TOP muxes. The consequence of this design if the fact that the TOP
part of the hierarchy has to be enabled permanently to ensure proper
operation of the SoC power related components (G3D power domain and
Exynos Power Management Unit for system suspend/resume).

This patch adds an explicit call to clk_prepare_enable() on the last MUX
in the TOP part of G3D clock hierarchy to keep it enabled permanently to
ensure that the internal busses get their clock regardless of the main
G3D clock enablement status.

This fixes following imprecise abort issue observed on Odroid XU3/XU4
after enabling Panfrost driver by commit 1a5a85c5 "ARM: dts: exynos:
Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"):

panfrost 11800000.gpu: clock rate = 400000000
panfrost 11800000.gpu: failed to get regulator: -517
panfrost 11800000.gpu: regulator init failed -517
Power domain G3D disable failed
...
panfrost 11800000.gpu: clock rate = 400000000
8<--- cut here ---
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
pgd = (ptrval)
[00000000] *pgd=00000000
Internal error: : 1406 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
Workqueue: events deferred_probe_work_func
PC is at panfrost_gpu_soft_reset+0x94/0x110
LR is at ___might_sleep+0x128/0x2dc
...
[<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c)
[<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc)
[<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178)
[<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c)
[<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474)
[<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc)
[<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8)
[<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c)
[<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90)
[<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0)
[<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864)
[<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0)
[<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160)
[<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
Exception stack(0xee03dfb0 to 0xee03dff8)
...
Code: e594300c e5933020 e3130c01 1a00000f (ebefff50).
---[ end trace badde2b74a65a540 ]---

In the above case, the Panfrost driver disables G3D clocks after failure
of getting the needed regulator and return with -EPROVE_DEFER code. This
causes G3D power domain disable failure and then, during second probe
an imprecise abort is triggered due to undefined power domain state.

Fixes: 45f10dab ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path")
Fixes: c9f7567a ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Link: https://lkml.kernel.org/r/20191216131407.17225-1-m.szyprowski@samsung.comAcked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.
Suggested-by: NMarian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Save and restore top PLL related configuration registers for big (APLL)
and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
were reset to default values after suspend/resume cycle and performance
after system resume was affected when performance governor has been selected.

Fixes: 77342432 ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: NMarian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add new table rate for VPLL for Exynos 542x SoC required to support
Mali GPU clock frequencies.
Signed-off-by: NMarian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Properly save and restore all top PLL related configuration registers
during suspend/resume cycle. So far driver only handled EPLL and RPLL
clocks, all other were reset to default values after suspend/resume cycle.
This caused for example lower G3D (MALI Panfrost) performance after system
resume, even if performance governor has been selected.
Reported-by: NReported-by: Marian Mihailescu <mihailescu2m@gmail.com>
Fixes: 77342432 ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

G3D clocks require special handling of their parent bus clock during power
domain on/off sequences. Those clocks were not initially added to the
sub-CMU handler, because that time there was no open-source driver for the
G3D (MALI Panfrost) hardware module and it was not possible to test it.

This patch fixes this issue. Parent clock for G3D hardware block is now
properly preserved during G3D power domain on/off sequence. This restores
proper MALI Panfrost performance broken by commit 8686764f
("ARM: dts: exynos: Add G3D power domain to Exynos542x").
Reported-by: NMarian Mihailescu <mihailescu2m@gmail.com>
Fixes: b06a532b ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: NMarian Mihailescu <mihailescu2m@gmail.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

M2M scaler clocks require special handling of their parent bus clock during
power domain on/off sequences. MSCL clocks were not initially added to the
sub-CMU handler, because that time there was no driver for the M2M scaler
device and it was not possible to test it.

This patch fixes this issue. Parent clock for M2M scaler devices is now
properly preserved during MSC power domain on/off sequence. This gives M2M
scaler devices proper performance: fullHD XRGB32 image 1000 rotations test
takes 3.17s instead of 45.08s.

Fixes: b06a532b ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Link: https://lkml.kernel.org/r/20190808121839.23892-1-m.szyprowski@samsung.comAcked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch fixes broken sound on Exynos5422/5800 platforms after
system/suspend resume cycle in cases where the audio root clock
is derived from MAU_EPLL_CLK.

In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux
during system suspend/resume cycle for Exynos5800 we group the MAU
block input clocks in "MAU" sub-CMU and add the clock mux control
bit to .suspend_regs.  This ensures that user configuration of the mux
is not lost after the PMU block changes the mux setting to OSC_DIV
when switching off the MAU power domain.

Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not
sufficient as at the time of the syscore_ops suspend call MAU power
domain is already turned off and we already save and subsequently
restore an incorrect register's value.

Fixes: b06a532b ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Reported-by: NJaafar Ali <jaafarkhalaf@gmail.com>
Suggested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: NJaafar Ali <jaafarkhalaf@gmail.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lkml.kernel.org/r/20190808144929.18685-2-s.nawrocki@samsung.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

In order to make it easier in subsequent patch to create different subcmu
lists for exynos5420 and exynos5800 SoCs the code is rewritten so we pass
an array of pointers to the subcmus initialization function.

Fixes: b06a532b ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Tested-by: NJaafar Ali <jaafarkhalaf@gmail.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lkml.kernel.org/r/20190808144929.18685-1-s.nawrocki@samsung.comReviewed-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NEnrico Weigelt <info@metux.net>
Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NLukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NLukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Ensure that clocks for core SoC modules (including TZPC0..9 modules)
are enabled for suspend/resume cycle. This fixes suspend/resume
support on Exynos5422-based Odroid XU3/XU4 boards.
Suggested-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <snawrocki@kernel.org>

The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on
exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to
handle the bit only on exynos5420.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
[m.szyprow: rewrote commit subject]
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <snawrocki@kernel.org>

Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <snawrocki@kernel.org>

Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This allows changing the EPLL output frequency through the audio subsystem
clock tree leaf clocks. This change is needed to support audio on the HDMI
interface on Peach-Pi(t) Chromebook.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Clocks related to DISP, GSC and MFC blocks require special handling for
power domain turn on/off sequences. Till now this was handled by Exynos
power domain driver, but that approach was limited only to some special
cases. This patch moves handling of those operations to clock controller
driver. This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5420 driver.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time validation.
The patch introduces such validators and expands all initializers
with additional input frequency parameter, required to validate rates.
Since S3C24xx PLLs requires different validators two new macros have
been introduced to deal with it. Also, since PLLs 4502 and 4508 have
different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE.

As the patch adds only compile time validators it should not have impact
on compiled code.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Drop clkdev alias for "mout_aclk400_mscl" clock. It was not used at all
and it was probably committed by accident.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The TOP "aclk400_mscl" clock should be kept enabled all the time
to allow proper access to power management control for MSC power
domain and devices that are a part of it. This change is required
for the scaler to work properly after domain power on/off sequence.

Fixes: 318fa46c ("clk/samsung: exynos542x: mark some clocks as critical")
Signed-off-by: NAndrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL
and the audio subsystem clock controller so that the EPLL's output
frequency can be set indirectly with clk_set_rate() on a leaf clock.
That should be safe as EPLL is normally only used to generate clock
for the audio subsystem.
With this change we can avoid passing the EPLL clock to the ASoC
machine driver.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Parent clock of the MAU_EPLL gate clock on exynos5422 is
"mout_user_mau_epll", not "mout_mau_epll_clk". This change
only affects exynos5422/5800.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch fixes values of the EPLL K coefficient and changes
the EPLL output frequency values to match exactly what is
possible to achieve with given M, P, S, K coefficients.
This allows to avoid rounding errors and unexpected frequency
being set with clk_set_rate(), due to recalc_rate returning
different values than the PLL rate specified in the
exynos5420_epll_24mhz_tbl table. E.g. this prevents a case
where two consecutive clk_set_rate() calls with same argument
result in different PLL output frequency.

The PLL output frequencies have been calculated with formula:

f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16

where fxtal = 24000000.

Fixes: 9842452a ("clk: samsung: exynos542x: Add EPLL rate table")
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Some parent clocks of the Exynos542x clock blocks, which have separate
power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always
enabled to access any register related to power management unit or devices
connected to it. For the time being, until a proper solution based on
runtime PM is applied, mark those clocks as critical (instead of ignore
unused or even no flags) to prevent disabling them.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express
Controller) which generates the clocks for DRAM and NoC (Network on Chip)
bus.  There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420
and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source
group.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The aclk333 clock needs to be ungated during the MFC power domain switch,
so set the clock ID to allow the Exynos power domain logic to lookup this
clock if is defined in the MFC PD device tree node.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The exynos5420_clk_sleep_init() function and arrays with initialization
data of PLLs can be moved to init section because they are referenced
only from other init-level symbols.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

All of initialization data can be made const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The samsung_clk_init() cannot return NULL. Either it returns allocated
memory or it panics.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds the clock id for ACLK clock which is source clock
of AMBA AXI bus. This clock should be handled in the bus frequency
scaling driver.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NMarkus Reichl <m.reichl@fivetechno.de>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This flag is a no-op now. Remove usage of the flag.
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are
using it. The clkdev.h header isn't always used either, so remove
it and add in slab.h where files were relying on it to include
slab for them.

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add missing static to local (file-scope only) symbols.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>