- 20 12月, 2013 1 次提交
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由 Laxman Dewangan 提交于
Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 17 12月, 2013 8 次提交
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由 Thierry Reding 提交于
This pin needs to be configured in pull-down, non-tristate mode in order for the backlight to work correctly. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Other boards use PULL_NONE for their debug UART pins, and without this change, the board doesn't accept any serial input. Don't set the I2S port pins to tristate mode, or no audio signal will be sent out. Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2") Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Subsequent patches will need to reference a PWM channel for backlight support, so enable the PWM device and assign a label to it. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com>
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由 Joseph Lo 提交于
This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: NJoseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 10月, 2013 1 次提交
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由 Joseph Lo 提交于
Enable LP1 suspend mode for Tegra124 Venice2 board. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 09 10月, 2013 1 次提交
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由 Joseph Lo 提交于
Add support for the Tegra124 based Venice2 reference board. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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