- 19 10月, 2017 2 次提交
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由 Linus Walleij 提交于
When making the pin control submenu globally visible, all kinds of oddities appear, in blackfin a few files were #including <linux/gpio.h> and relying on that to pull in <asm/gpio.h>. This was not working when pin control but not GPIOLIB was selected resulting in a breakage in allmodconfig. The code these files were using was still there and defined in <asm/gpio.h> just not pulle in from just including <linux/gpio.h> Simply add the required includes explicitly in the blackfin kernel core and everything compiles fine. Delete the use of the incorrect <linux/gpio.h> where possible. Add stubs to <asm/gpio.h> for the functions called from PM: these should probably also depend on !PINCTRL but since the global CONFIG_PM symbol is used to compile PM support, we need some more intrusive thing here, to be tested by Blackfin maintainers. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(®s->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(®s->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 10月, 2017 4 次提交
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由 Linus Walleij 提交于
The SX150X driver was moved over to pin control a while back. The GPIO Kconfig symbol creates a circular dependency since it requires GPIOLIB and the pin control driver selects GPIOLIB so get rid of the old annoying Kconfig option. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Miquel Raynal 提交于
Fix a typo in A37xx pin controllers documentation about uart2 pin group. Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 10月, 2017 1 次提交
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由 Linus Walleij 提交于
Some two functions were missing from the Gemini pin control driver. Noticed when trying to use ethernet. Fix it up by adding them. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 10月, 2017 1 次提交
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由 Linus Walleij 提交于
Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 10月, 2017 8 次提交
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由 Fenglin Wu 提交于
GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is configured. Update is_enabled flag in config_set() so that it can reflect GPIO status correctly. Also modify EN_CTL register based on is_enabled flag in config_set() to configure the GPIO properly. Signed-off-by: NFenglin Wu <fenglinw@codeaurora.org> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Phil Reid 提交于
Variable mask and val are not used in the mcp_pinconf_set(). Signed-off-by: NPhil Reid <preid@electromag.com.au> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Phil Reid 提交于
This adds the compatible string for the mcp23018, which is the i2c variant of the mcp23s18. Signed-off-by: NPhil Reid <preid@electromag.com.au> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Lars Poeschel 提交于
The mcp23s08 driver moved to pinctrl recently. It accepts the bias-pull-up pinctrl property since then. This updates the binding doc to reflect that. Thanks to Sebastian Reichel for the working example. Signed-off-by: NLars Poeschel <poeschel@lemonage.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Lars Poeschel 提交于
The mcp23s08 driver was moved from gpio to pinctrl. This moves it's devicetree binding doc as well. So driver and binding doc are in sync again. Signed-off-by: NLars Poeschel <poeschel@lemonage.de> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Phil Reid 提交于
This allows PINCTRL to be selected manually to allow enabling of the mcp23s08 i2c/spi gpio driver. Which is not platform specific. Signed-off-by: NPhil Reid <preid@electromag.com.au> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
While removing the need to have pin_base defined in meson pinctrl drivers, I forgot to remove the corresponding field from the pinctrl_data structure. Fixing this now. Fixes: 70e5ecb1 ("pinctrl: meson: get rid of pin_base") Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
Add TEST_N pinmux for channel 6 and 7 of the i2s output Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 10月, 2017 2 次提交
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由 Colin Ian King 提交于
The structure sx150x_regmap_config is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'sx150x_regmap_config' was not declared. Should it be static? Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Colin Ian King 提交于
The function ingenic_pinctrl_probe is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warnings symbol 'ingenic_pinctrl_probe' was not declared. Should it be static? Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 08 10月, 2017 1 次提交
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由 Geert Uytterhoeven 提交于
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 10月, 2017 7 次提交
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由 Linus Walleij 提交于
Merge tag 'sh-pfc-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 - Add SDHI and DRIF pin groups on R-Car H3 ES2.0, - Add USB3.0 host pin groups on R-Car H3 (ES1.x and ES2.0), - Add EthernetAVB and USB2.0 host pin groups on R-Car D3.
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由 David Wu 提交于
If the gmac-m1 optimization(bit10) is selected, the gpio function of gmac pins is not valid. We may use the rmii mode for gmac interface, the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, and gmac_rxd0m3 select bit10 is more correct. Signed-off-by: NDavid Wu <david.wu@rock-chips.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 David Wu 提交于
The offset of gpio0 and gpio1 bank drive strength is 0x8, not 0x4. But the mux is 0x4, we couldn't use the IOMUX_WIDTH_4BIT flag, so we give them actual offset. Signed-off-by: NDavid Wu <david.wu@rock-chips.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
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由 Linus Walleij 提交于
These request/free functions are just reimplementations of the standard helpers in gpiolib. Delete them and replace with the helpers. Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
These request/free functions are just reimplementations of the standard helpers in gpiolib. Delete them and replace with the helpers. Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
These request/free functions are just reimplementations of the standard helpers in gpiolib. Delete them and replace with the helpers. Acked-by: NScott Branden <scott.branden@broadcom.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 10月, 2017 4 次提交
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由 Jerome Brunet 提交于
GPIOX_22 is declared as a gpio but the id is no present in the pin table. This hole trigger an error while reading the pingroup debugfs entry GPIOX_22 is no routed externally. For all we know, it could an internal pin of SoC Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
On meson-gx platforms, TEST_N has been incorrectly declared in the EE controller while it belongs to AO controller. Move the pin to the appropriate controller Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
pin_base was used with the manually set pin offset in meson pinctrl. This is no longer the case, pin_base is 0 on every meson pinctrl controllers and should go away. Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jerome Brunet 提交于
Offset on meson pinctrl and gpios is something that was carried from the vendor driver, where there is a weird link between the 2 controllers. Since these 2 controllers are independent, this offset adds an unnecessary complexity. This patch remove this manually set offset and rely on pinctrl to figure out the gpio base offset Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 02 10月, 2017 2 次提交
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由 Takeshi Kihara 提交于
This patch adds USB3.0 ch0 pinmux support to R8A7795 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch adds USB3{0,1} (USB3.0 host) pinmux support to R8A7795 ES1.x SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 27 9月, 2017 1 次提交
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由 Chris Gorman 提交于
Fixed typo on comment for north_community. Signed-off-by: NChris Gorman <chrisjohgorman@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 9月, 2017 1 次提交
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由 Linus Walleij 提交于
The pinctrl_request_gpio() and pinctrl_free_gpio() break the nice namespacing in the other cross-calls like pinctrl_gpio_foo(). Just rename them and all references so we have one namespace with all cross-calls under pinctrl_gpio_*(). Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 9月, 2017 3 次提交
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由 Jerome Brunet 提交于
ENOSYS is special and should only be used for incorrect syscall number. It is not the case here. let's use ENOTSUPP instead. Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Colin Ian King 提交于
Don't populate the read-only arrays prop2 and prop4 on the stack, instead make them static const. Makes the object code smaller by over 230 bytes: Before: text data bss dec hex filename 28235 5820 192 34247 85c7 drivers/pinctrl/pinctrl-single.o After: text data bss dec hex filename 27839 5980 192 34011 84db drivers/pinctrl/pinctrl-single.o Signed-off-by: NColin Ian King <colin.king@canonical.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Colin Ian King 提交于
The functions amd_gpio_suspend and amd_gpio_resume are local to the source and do not need to be in global scope, so make them static. Cleans up sparse warnings: symbol 'amd_gpio_suspend' was not declared. Should it be static? symbol 'amd_gpio_resume' was not declared. Should it be static? Signed-off-by: NColin Ian King <colin.king@canonical.com> Reviewed-by: NDaniel Drake <drake@endlessm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 9月, 2017 3 次提交
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由 Takeshi Kihara 提交于
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Yoshihiro Shimoda 提交于
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Dirk Behme 提交于
DRIF support for r8a7795 was initially added with commit 2d775831 ("pinctrl: sh-pfc: r8a7795: Add DRIF support") and later dropped from the new pfc-r8a7795.c while re-naming the initial pfc-r8a7795.c to pfc-r8a7795-es1.c in commit b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0"). As the DRIF doesn't differ, re-add it here. Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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