- 23 11月, 2021 2 次提交
-
-
由 Ansuel Smith 提交于
Add LAG support to this switch. In Documentation this is described as trunk mode. A max of 4 LAGs are supported and each can support up to 4 port. The current tx mode supported is Hash mode with both L2 and L2+3 mode. When no port are present in the trunk, the trunk is disabled in the switch. When a port is disconnected, the traffic is redirected to the other available port. The hash mode is global and each LAG require to have the same hash mode set. To change the hash mode when multiple LAG are configured, it's required to remove each LAG and set the desired hash mode to the last. An error is printed when it's asked to set a not supported hadh mode. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
The switch supports mirror mode. Only one port can set as mirror port and every other port can set to both ingress and egress mode. The mirror port is disabled and reverted to normal operation once every port is removed from sending packet to it. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 22 11月, 2021 9 次提交
-
-
由 Ansuel Smith 提交于
Add support for mdb add/del function. The ARL table is used to insert the rule. The rule will be searched, deleted and reinserted with the port mask updated. The function will check if the rule has to be updated or insert directly with no deletion of the old rule. If every port is removed from the port mask, the rule is removed. The rule is set STATIC in the ARL table (aka it doesn't age) to not be flushed by fast age function. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
qca8k support setting ageing time in step of 7s. Add support for it and set the max value accepted of 7645m. Documentation talks about support for 10000m but that values doesn't make sense as the value doesn't match the max value in the reg. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
The switch supports fast aging by flushing any rule in the ARL table for a specific port. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
We are currently missing 2 additionals MIB counter present in QCA833x switch. QC832x switch have 39 MIB counter and QCA833X have 41 MIB counter. Add the additional MIB counter and rework the MIB function to print the correct supported counter from the match_data struct. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Convert any qca8k set/clear/pool to regmap helper and add missing config to regmap_config struct. Read/write/rmw operation are reworked to use the regmap helper internally to keep the delta of this patch low. These additional function will then be dropped when the code split will be proposed. Ipq40xx SoC have the internal switch based on the qca8k regmap but use mmio for read/write/rmw operation instead of mdio. In preparation for the support of this internal switch, convert the driver to regmap API to later split the driver to common and specific code. The overhead introduced by the use of regamp API is marginal as the internal mdio will bypass it by using its direct access and regmap will be used only by configuration functions or fdb access. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
In preparation for regmap conversion, move regmap init in the probe function and make it mandatory as any read/write/rmw operation will be converted to regmap API. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Mutex is already init in sw_probe. Remove the extra init in qca8k_setup. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Convert and try to standardize bit fields using GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the standard macro and tidy things up. No functional change intended. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
The very next check for port 0 and 6 already makes sure we don't go out of bounds with the ports_config delay table. Remove the redundant check. Reported-by: Nkernel test robot <lkp@intel.com> Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 03 11月, 2021 1 次提交
-
-
由 Ansuel Smith 提交于
Some device set MAC06 exchange in the bootloader. This cause some problem as we don't support this strange mode and we just set the port6 as the primary CPU port. With MAC06 exchange, PAD0 reg configure port6 instead of port0. Add an extra check and explicitly disable MAC06 exchange to correctly configure the port PAD config. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Fixes: 3fcf734a ("net: dsa: qca8k: add support for cpu port 6") Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 20 10月, 2021 1 次提交
-
-
由 Ansuel Smith 提交于
Tidy and organize qca8k setup function from multiple for loop. Change for loop in bridge leave/join to scan all port and skip cpu port. No functional change intended. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 18 10月, 2021 1 次提交
-
-
由 Ansuel Smith 提交于
Fix delay settings applied to wrong cpu in parse_port_config. The delay values is set to the wrong index as the cpu_port_index is incremented too early. Start the cpu_port_index to -1 so the correct value is applied to address also the case with invalid phy mode and not available port. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 15 10月, 2021 9 次提交
-
-
由 Ansuel Smith 提交于
Move ports related config to dedicated struct to keep things organized. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
QCA original code report port instability and sa that SGMII also require to set internal delay. Generalize the rgmii delay function and apply the advised value if they are not defined in DT. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
QCA8328 switch is the bigger brother of the qca8327. Same regs different chip. Change the function to set the correct pin layout and introduce a new match_data to differentiate the 2 switch as they have the same ID and their internal PHY have the same ID. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Some qca8327 switch require to force the ignore of power on sel strapping. Some switch require to set the led open drain mode in regs instead of using strapping. While most of the device implements this using the correct way using pin strapping, there are still some broken device that require to be set using sw regs. Introduce a new binding and support these special configuration. As led open drain require to ignore pin strapping to work, the probe fails with EINVAL error with incorrect configuration. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Support enabling PLL on the SGMII CPU port. Some device require this special configuration or no traffic is transmitted and the switch doesn't work at all. A dedicated binding is added to the CPU node port to apply the correct reg on mac config. Fail to correctly configure sgmii with qca8327 switch and warn if pll is used on qca8337 with a revision greater than 1. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Future proof commit. This switch have 2 CPU ports and one valid configuration is first CPU port set to sgmii and second CPU port set to rgmii-id. The current implementation detects delay only for CPU port zero set to rgmii and doesn't count any delay set in a secondary CPU port. Drop the current delay scan function and move it to the sgmii parser function to generalize and implicitly add support for secondary CPU port set to rgmii-id. Introduce new logic where delay is enabled also with internal delay binding declared and rgmii set as PHY mode. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Currently CPU port is always hardcoded to port 0. This switch have 2 CPU ports. The original intention of this driver seems to be use the mac06_exchange bit to swap MAC0 with MAC6 in the strange configuration where device have connected only the CPU port 6. To skip the introduction of a new binding, rework the driver to address the secondary CPU port as primary and drop any reference of hardcoded port. With configuration of mac06 exchange, just skip the definition of port0 and define the CPU port as a secondary. The driver will autoconfigure the switch to use that as the primary CPU port. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Add support for this in the qca8k driver. Also add support for SGMII rx/tx clock falling edge. This is only present for pad0, pad5 and pad6 have these bit reserved from Documentation. Add a comment that this is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and setting falling in port0 applies to both configuration with sgmii used for port0 or port6. Co-developed-by: NMatthew Hagan <mnhagan88@gmail.com> Signed-off-by: NMatthew Hagan <mnhagan88@gmail.com> Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Add missing mac power sel support needed for ipq8064/5 SoC that require 1.8v for the internal regulator port instead of the default 1.5v. If other device needs this, consider adding a dedicated binding to support this. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 19 9月, 2021 1 次提交
-
-
由 Vladimir Oltean 提交于
Lino reports that on his system with bcmgenet as DSA master and KSZ9897 as a switch, rebooting or shutting down never works properly. What does the bcmgenet driver have special to trigger this, that other DSA masters do not? It has an implementation of ->shutdown which simply calls its ->remove implementation. Otherwise said, it unregisters its network interface on shutdown. This message can be seen in a loop, and it hangs the reboot process there: unregister_netdevice: waiting for eth0 to become free. Usage count = 3 So why 3? A usage count of 1 is normal for a registered network interface, and any virtual interface which links itself as an upper of that will increment it via dev_hold. In the case of DSA, this is the call path: dsa_slave_create -> netdev_upper_dev_link -> __netdev_upper_dev_link -> __netdev_adjacent_dev_insert -> dev_hold So a DSA switch with 3 interfaces will result in a usage count elevated by two, and netdev_wait_allrefs will wait until they have gone away. Other stacked interfaces, like VLAN, watch NETDEV_UNREGISTER events and delete themselves, but DSA cannot just vanish and go poof, at most it can unbind itself from the switch devices, but that must happen strictly earlier compared to when the DSA master unregisters its net_device, so reacting on the NETDEV_UNREGISTER event is way too late. It seems that it is a pretty established pattern to have a driver's ->shutdown hook redirect to its ->remove hook, so the same code is executed regardless of whether the driver is unbound from the device, or the system is just shutting down. As Florian puts it, it is quite a big hammer for bcmgenet to unregister its net_device during shutdown, but having a common code path with the driver unbind helps ensure it is well tested. So DSA, for better or for worse, has to live with that and engage in an arms race of implementing the ->shutdown hook too, from all individual drivers, and do something sane when paired with masters that unregister their net_device there. The only sane thing to do, of course, is to unlink from the master. However, complications arise really quickly. The pattern of redirecting ->shutdown to ->remove is not unique to bcmgenet or even to net_device drivers. In fact, SPI controllers do it too (see dspi_shutdown -> dspi_remove), and presumably, I2C controllers and MDIO controllers do it too (this is something I have not researched too deeply, but even if this is not the case today, it is certainly plausible to happen in the future, and must be taken into consideration). Since DSA switches might be SPI devices, I2C devices, MDIO devices, the insane implication is that for the exact same DSA switch device, we might have both ->shutdown and ->remove getting called. So we need to do something with that insane environment. The pattern I've come up with is "if this, then not that", so if either ->shutdown or ->remove gets called, we set the device's drvdata to NULL, and in the other hook, we check whether the drvdata is NULL and just do nothing. This is probably not necessary for platform devices, just for devices on buses, but I would really insist for consistency among drivers, because when code is copy-pasted, it is not always copy-pasted from the best sources. So depending on whether the DSA switch's ->remove or ->shutdown will get called first, we cannot really guarantee even for the same driver if rebooting will result in the same code path on all platforms. But nonetheless, we need to do something minimally reasonable on ->shutdown too to fix the bug. Of course, the ->remove will do more (a full teardown of the tree, with all data structures freed, and this is why the bug was not caught for so long). The new ->shutdown method is kept separate from dsa_unregister_switch not because we couldn't have unregistered the switch, but simply in the interest of doing something quick and to the point. The big question is: does the DSA switch's ->shutdown get called earlier than the DSA master's ->shutdown? If not, there is still a risk that we might still trigger the WARN_ON in unregister_netdevice that says we are attempting to unregister a net_device which has uppers. That's no good. Although the reference to the master net_device won't physically go away even if DSA's ->shutdown comes afterwards, remember we have a dev_hold on it. The answer to that question lies in this comment above device_link_add: * A side effect of the link creation is re-ordering of dpm_list and the * devices_kset list by moving the consumer device and all devices depending * on it to the ends of these lists (that does not happen to devices that have * not been registered when this function is called). so the fact that DSA uses device_link_add towards its master is not exactly for nothing. device_shutdown() walks devices_kset from the back, so this is our guarantee that DSA's shutdown happens before the master's shutdown. Fixes: 2f1e8ea7 ("net: dsa: link interfaces with the DSA master to get rid of lockdep warnings") Link: https://lore.kernel.org/netdev/20210909095324.12978-1-LinoSanfilippo@gmx.de/Reported-by: NLino Sanfilippo <LinoSanfilippo@gmx.de> Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 12 9月, 2021 1 次提交
-
-
由 Ansuel Smith 提交于
When the mdio legacy mapping is used the mii_bus priv registered by DSA refer to the dsa switch struct instead of the qca8k_priv struct and causes a kernel panic. Create dedicated function when the internal dedicated mdio driver is used to properly handle the 2 different implementation. Fixes: 759bafb8 ("net: dsa: qca8k: add support for internal phy and internal mdio") Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 10 6月, 2021 2 次提交
-
-
由 Dan Carpenter 提交于
This code check "reg" but "ret" was intended so the error handling will never trigger. Fixes: 7c9896e3 ("net: dsa: qca8k: check return value of read functions correctly") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Dan Carpenter 提交于
The "hi" variable is a u64 but the qca8k_read() writes to the top 32 bits of it. That will work on little endian systems but it's a bit subtle. It's cleaner to make declare "hi" as a u32. We will still need to cast it when we shift it later on in the function but that's fine. Fixes: 7c9896e3 ("net: dsa: qca8k: check return value of read functions correctly") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 31 5月, 2021 2 次提交
-
-
由 Yang Yingliang 提交于
Now we can check qca8k_read() return value correctly, so if it fails, we need return directly. Signed-off-by: NYang Yingliang <yangyingliang@huawei.com> Signed-off-by: NJakub Kicinski <kuba@kernel.org>
-
由 Yang Yingliang 提交于
Current return type of qca8k_mii_read32() and qca8k_read() are unsigned, it can't be negative, so the return value check is unuseful. For check the return value correctly, change return type of the read functions and add a output parameter to store the read value. Signed-off-by: NYang Yingliang <yangyingliang@huawei.com> Signed-off-by: NJakub Kicinski <kuba@kernel.org>
-
- 19 5月, 2021 1 次提交
-
-
由 Wei Yongjun 提交于
Add the missing unlock before return from function qca8k_vlan_add() and qca8k_vlan_del() in the error handling case. Fixes: 028f5f8e ("net: dsa: qca8k: handle error with qca8k_read operation") Reported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
- 15 5月, 2021 10 次提交
-
-
由 Ansuel Smith 提交于
Define get_phy_flags to pass switch_Revision needed to tweak the internal PHY with debug values based on the revision. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Improve the internal mdio read/write bus access by caching the value without accessing it for every read/write. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Add support to setup_mdio_bus for internal phy declaration. Introduce a flag to use the legacy port phy mapping by default and use the direct mapping if a mdio node is detected in the switch node. Register a dedicated mdio internal mdio bus to address the different mapping between port and phy if the mdio node is detected. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
The witch require some extra delay after setting page or the next read/write can use still use the old page. Add a delay after the set_page function to address this as it's done in QSDK legacy driver. Some timeouts were notice with VLAN and phy function, enlarge the mdio busy wait timeout to fix these problems. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
MDIO_MASTER operation have a dedicated busy wait that is not protected by the mdio mutex. This can cause situation where the MASTER operation is done and a normal operation is executed between the MASTER read/write and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to address this issue by binding the lock for the whole MASTER operation and not only the mdio read/write common operation. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Also on driver remove the MASTER_CTRL can be left set and cause the malfunction of any next driver using the mdio device. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
The legacy qsdk code used a different delay instead of the max value. Qsdk use 1 ns for rx and 2 ns for tx. Make these values configurable using the standard rx/tx-internal-delay-ps ethernet binding and apply qsdk values by default. The connected gmac doesn't add any delay so no additional delay is added to tx/rx. On this switch the delay is actually in ns so value should be in the 1000 order. Any value converted from ps to ns by dividing it by 1000 as the switch max value for delay is 3ns. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Dsa now also supports ethernet-ports. Add this new binding as a fallback if the ports node can't be found. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
qca8k internal phy driver require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-
由 Ansuel Smith 提交于
Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. Signed-off-by: NAnsuel Smith <ansuelsmth@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
-