1. 28 4月, 2008 2 次提交
  2. 16 4月, 2008 3 次提交
  3. 11 4月, 2008 1 次提交
  4. 09 4月, 2008 3 次提交
  5. 14 3月, 2008 2 次提交
  6. 05 3月, 2008 1 次提交
  7. 24 2月, 2008 2 次提交
    • N
      spi: pxa2xx_spi clock polarity fix · b97c74bd
      Ned Forrester 提交于
      Fixes a sequencing bug in spi driver pxa2xx_spi.c in which the chip select
      for a transfer may be asserted before the clock polarity is set on the
      interface.  As a result of this bug, the clock signal may have the wrong
      polarity at transfer start, so it may need to make an extra half transition
      before the intended clock/data signals begin.  (This probably means all
      transfers are one bit out of sequence.)
      
      This only occurs on the first transfer following a change in clock polarity
      in systems using more than one more than one such polarity.  The fix
      assures that the clock mode is properly set before asserting chip select.
      
      This bug was introduced in a patch merged on 2006/12/10, kernel 2.6.20.
      The patch defines an additional bit in: include/asm-arm/arch-pxa/regs-ssp.h
      for 2.6.25 and newer kernels but this addition must be made in:
      include/asm-arm/arch-pxa/pxa-regs.h for kernels between 2.6.20 and 2.6.24,
      inclusive
      Signed-off-by: NNed Forrester <nforrester@whoi.edu>
      Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Cc: <stable@kernel.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b97c74bd
    • A
      atmel_spi: fix clock polarity · f6febccd
      Atsushi Nemoto 提交于
      The atmel_spi driver does not initialize clock polarity correctly (except for
      at91rm9200 CS0 channel) in some case.
      
      The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock signal
      is controlled by CSRn.CPOL bit, but this register controls clock signal
      correctly only in 'real transfer' duration.  At the time of cs_activate()
      call, CSRn.CPOL will be initialized correctly, but the controller do not know
      which channel is to be used next, so clock signal will stay at the inactive
      state of last transfer.  If clock polarity of new transfer and last transfer
      was differ, new transfer will start with wrong clock signal state.
      
      For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0 or 1
      transfer, the clock signal state at the assertion of chipselect will be low.
      Of course this will violates SPI transfer.
      
      This patch is short term solution for this problem.  It makes all CSRn.CPOL
      match for the transfer before activating chipselect.  For longer term, the
      best fix might be to let NPCS0 stay selected permanently in MR and overwrite
      CSR0 with to the new slave's settings before asserting CS.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Acked-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
      Cc: David Brownell <david-b@pacbell.net>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f6febccd
  8. 07 2月, 2008 16 次提交
  9. 03 2月, 2008 1 次提交
  10. 28 1月, 2008 1 次提交
  11. 27 1月, 2008 2 次提交
  12. 26 1月, 2008 2 次提交
  13. 25 1月, 2008 2 次提交
  14. 19 1月, 2008 1 次提交
  15. 09 1月, 2008 1 次提交