1. 17 12月, 2019 1 次提交
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      bus: ti-sysc: Fix iterating over clocks · 2c81f0f6
      Tony Lindgren 提交于
      Commit d878970f ("bus: ti-sysc: Add separate functions for handling
      clocks") separated handling of optional clocks from the main clocks, but
      introduced an issue where we do not necessarily allocate a slot for both
      fck and ick clocks, but still assume fixed slots for enumerating over the
      clocks.
      
      Let's fix the issue by ensuring we always have slots for both fck and ick
      even if we don't use ick, and don't attempt to enumerate optional clocks
      if not allocated.
      
      In the long run we might want to simplify things a bit by only allocating
      space only for the optional clocks as we have only few devices with
      optional clocks.
      
      Fixes: d878970f ("bus: ti-sysc: Add separate functions for handling clocks")
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      2c81f0f6
  2. 13 12月, 2019 1 次提交
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      bus: ti-sysc: Fix missing reset delay handling · e709ed70
      Tony Lindgren 提交于
      We have dts property for "ti,sysc-delay-us", and we're using it, but the
      wait after OCP softreset only happens if devices are probed in legacy mode.
      
      Let's add a delay after writing the OCP softreset when specified.
      
      Fixes: e0db94fe ("bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits")
      Cc: Keerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e709ed70
  3. 10 12月, 2019 1 次提交
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      bus: ti-sysc: Fix missing force mstandby quirk handling · 93c60483
      Tony Lindgren 提交于
      Commit 03856e92 ("bus: ti-sysc: Handle mstandby quirk and use it for
      musb") added quirk handling for mstandby quirk but did not consider that
      we also need a quirk variant for SYSC_QUIRK_FORCE_MSTANDBY.
      
      We need to use forced idle mode for both SYSC_QUIRK_SWSUP_MSTANDBY and
      SYSC_QUIRK_FORCE_MSTANDBY, but SYSC_QUIRK_SWSUP_MSTANDBY also need to
      additionally also configure no-idle mode when enabled.
      
      Fixes: 03856e92 ("bus: ti-sysc: Handle mstandby quirk and use it for musb")
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      93c60483
  4. 15 11月, 2019 2 次提交
  5. 22 10月, 2019 2 次提交
  6. 18 10月, 2019 1 次提交
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      bus: ti-sysc: Fix watchdog quirk handling · c7d8669f
      Tony Lindgren 提交于
      I noticed that when probed with ti-sysc, watchdog can trigger on am3, am4
      and dra7 causing a device reset.
      
      Turns out I made several mistakes implementing the watchdog quirk handling:
      
      1. We must do both writes to spr register
      
      2. We must also call the reset quirk on disable
      
      3. On am3 and am4 we need to also set swsup quirk flag
      
      I probably only tested this earlier with watchdog service running when the
      watchdog never gets disabled.
      
      Fixes: 4e23be47 ("bus: ti-sysc: Add support for module specific reset quirks")
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      c7d8669f
  7. 08 10月, 2019 3 次提交
  8. 07 9月, 2019 1 次提交
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      bus: ti-sysc: Remove unpaired sysc_clkdm_deny_idle() · a4c8723a
      Tony Lindgren 提交于
      Commit d098913a ("bus: ti-sysc: Fix clock handling for no-idle
      quirks") fixed handling for no-idle quirk modules that are not enabled
      by the bootloader.
      
      But it also caused unpaired clockdomain calls that won't allow idling
      the system. That's because clkdm_allow_idle_nolock() and
      clkdm_deny_idle_nolock() have usage count with clkdm->forcewake_count.
      
      Let's drop the unpaired sysc_clkdm_deny_idle() to fix idling of devices.
      
      Fixes: d098913a ("bus: ti-sysc: Fix clock handling for no-idle quirks")
      Cc: Keerthy <j-keerthy@ti.com>
      Cc: Vignesh Raghavendra <vigneshr@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      a4c8723a
  9. 06 9月, 2019 1 次提交
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      bus: ti-sysc: Fix handling of invalid clocks · 2783d063
      Tony Lindgren 提交于
      We can currently get "Unable to handle kernel paging request at
      virtual address" for invalid clocks with dts node but no driver:
      
      (__clk_get_hw) from [<c0138ebc>] (ti_sysc_find_one_clockdomain+0x18/0x34)
      (ti_sysc_find_one_clockdomain) from [<c0138f0c>] (ti_sysc_clkdm_init+0x34/0xdc)
      (ti_sysc_clkdm_init) from [<c0584660>] (sysc_probe+0xa50/0x10e8)
      (sysc_probe) from [<c065c6ac>] (platform_drv_probe+0x58/0xa8)
      
      Let's add IS_ERR checks to ti_sysc_clkdm_init() as And let's start treating
      clk_get() with -ENOENT as a proper error. If the clock name is specified
      in device tree we must succeed with clk_get() to continue. For modules with
      no clock names specified in device tree we will just ignore the clocks.
      
      Fixes: 2b2f7def ("bus: ti-sysc: Add support for missing clockdomain handling")
      Acked-by: NRoger Quadros <rogerq@ti.com>
      Tested-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      2783d063
  10. 05 9月, 2019 1 次提交
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      bus: ti-sysc: Fix clock handling for no-idle quirks · d098913a
      Tony Lindgren 提交于
      NFSroot can fail on dra7 when cpsw is probed using ti-sysc interconnect
      target module driver as reported by Keerthy.
      
      Device clocks and the interconnect target module may or may not be
      enabled by the bootloader on init, but we currently assume the clocks
      and module are on from the bootloader for "ti,no-idle" and
      "ti,no-idle-on-init" quirks as reported by Grygorii Strashko.
      
      Let's fix the issue by always enabling clocks init, and
      never disable them for "ti,no-idle" quirk. For "ti,no-idle-on-init"
      quirk, we must decrement the usage count later on to allow PM
      runtime to idle the module if requested.
      
      Fixes: 1a5cd7c2 ("bus: ti-sysc: Enable all clocks directly during init to read revision")
      Cc: Keerthy <j-keerthy@ti.com>
      Cc: Vignesh Raghavendra <vigneshr@ti.com>
      Reported-by: NKeerthy <j-keerthy@ti.com>
      Reported-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      d098913a
  11. 26 8月, 2019 3 次提交
  12. 13 8月, 2019 7 次提交
  13. 24 7月, 2019 3 次提交
  14. 10 6月, 2019 1 次提交
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      bus: ti-sysc: Add support for module specific reset quirks · 4e23be47
      Tony Lindgren 提交于
      Some older interconnect target modules need module internal clock
      toggling quirks to reset properly. We've been doing this in the
      platform code earlier, but need to be able to it directly in the
      ti-sysc driver when we no longer rely on on the platform code.
      
      Let's add reset handling for 1-wire, i2c and watchdog. Later on
      we can add more modules like msdi and dss as they get tested.
      For dra7 pcie, we should be able to just use the rstctrl reset
      driver when available.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      4e23be47
  15. 28 5月, 2019 11 次提交
  16. 02 5月, 2019 1 次提交
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      bus: ti-sysc: Handle devices with no control registers · e4f50c8d
      Tony Lindgren 提交于
      Some interconnect target modules have no module control registers at
      all, such as d_can on am335x and am437x.
      
      The d_can register offset at 0 is CTL register with 0x401 as the default
      value. I guess I mistook the 0x401 value for a revision register as the
      value happens to look similar to what the revision registers typically
      have for other modules.
      
      To handle modules with no control registers, we need to improve the
      ti-sysc driver a bit to bail out with errors on no control registers,
      and then we can remove the bogus revision registers for d_can.
      
      Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      Tested-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e4f50c8d