• T
    bus: ti-sysc: Do rstctrl reset handling in two phases · ea5a2e4d
    Tony Lindgren 提交于
    We need to deassert rstctrl resets before enabling clocks to avoid clock
    "failed to enable" errors. For asserting rstctrl reset, the clocks need
    to be enabled.
    
    As the reset controller status is not available for arrays, let's use
    devm_reset_control_get_optional() so we can get the status after reset.
    
    Note that depends on a proper PRM rstctrl driver, so far I've only
    tested this with earlier reset-simple patches.
    Tested-by: NKeerthy <j-keerthy@ti.com>
    Signed-off-by: NTony Lindgren <tony@atomide.com>
    ea5a2e4d
ti-sysc.c 56.2 KB