Add alias for FEC ethernet on i.MX to allow bootloaders (like U-Boot)
patch-in the MAC address for FEC using this alias.
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Per bindings of fixed-clock, #clock-cells is a required property.  Let's
add it for those fixed rate clocks.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Those two properties should have been set to zero, which
is the same as not specifying them.

Having address-cells set to 1 causes OF interrupt
mapping routines to add 1 to the interrupt-cells
property and as result fail because all calculations
are off by one.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX6SL EVK board has a 3*3 keypad matrix to support 8 keypads,
enable them, the keymap is as below:

SW6:  MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
SW7:  MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
SW8:  MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
SW9:  MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
SW10: MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
SW11: MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
SW12: MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
SW13: MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add ocram device support on i.MX6SL.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add anatop phandle for usbphy
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Instead of calling the regulator for the ARM core as 'cpu', let's rename it
as 'vddarm', so that we keep a better consistency with the other internal
regulators:

vdd1p1: 800 <--> 1375 mV at 1100 mV
vdd3p0: 2800 <--> 3150 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2400 mV
vddarm: 725 <--> 1450 mV at 1150 mV
vddpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1200 mV
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Device tree for iMX6SL doesn't have an existing cpu frequency table
as well as the VDDSOC/PU.
Signed-off-by: NJohn Tobias <john.tobias.ph@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Make the interrupts node slightly more readable.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts.  However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected.  This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board.  It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.

The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral.  Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This reverts commit b1d27c79.

Previously we switched the SSI scriprt to dual-fifo mode to reduce playback
underrun issue, which is only included by SDMA firmware version 2. However,
there are quite a lot people still using version 1 or default firmware in
the ROM code of SoC while these two kinds of firmwares do not support the
dual-fifo script and the audio function on their platform would be broken.

Thus this patch provisionally reverts the dual-fifo script to the original
single fifo script to meet all kinds of users' requirements, including the
version 1/2 or inner ROM firmware.
Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Use dual-fifo sdma scripts instead of shared scripts for ssi on i.MX series.
Signed-off-by: NNicolin Chen <b42378@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The imx6sl iomuxc syscon is compatible to imx6q, so let's add
compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This is needed for SD3.0 cards working on UHS mode.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add spi aliases.

While at it, keep the aliases entries sorted.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Enable USB function for OTG 1 and OTG 2 at mx6sololite evk.
Besides, fix the wrong interrupt number for OTG2 and host 1.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add iomuxc gpr device node for imx6sl.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There is no imx6sl specific sdma firmware.  Instead, imx6sl reuses
imx6q sdma firmware.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Updates SSI nodes to adopt generic DMA bindings.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the dma property for all the uart.

Note: Add the dma property does not mean we enable the dma for this
uart.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

In order to enable the DMA for some uart port in imx6sl, we add the
"fsl,imx6q-uart" to the uart's compatible property.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the #dma-cells property for all the sdma in all the imx platforms.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add SoC level device tree source for imx6sl.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Configure the data and tag latency for the L2 cache. This improves the
system performance.

This configuration is taken from Freescale's kernel patch

"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]

which does

writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

In this patch we are doing the same via the device tree.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1

The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add ldb device tree node and clock lookups.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 already has a devicetree node for the GPT, but not yet
has the clocks. Add them.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Replace /include/ (dtc) with #include (C pre-processor) for all imx DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as pinctrl settings. Use of those
features will increase the readability of the device tree files.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add ARM Cortex A9 Performance Monitor Unit (PMU) support.
On i.MX6 a combined interrupt on hardware line #126 is used
(i.MX6 TRM: Performance Unit interrupt).

For more details see Documentation/devicetree/bindings/arm/pmu.txt
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver.  However, the commit
bd603455 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree.  It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.

 smp_twd: clock not found -2
 ...
 Calibrating local timer... 396.13MHz.

Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add generic DMA device tree binding for mxs-dma.  The changes include:

 * Add channel interrupts into DMA controller nodes
 * Add properties '#dma-cells' and 'dma-channels' for DMA controller nodes
 * And properties 'dmas' and 'dma-names' for DMA client nodes
 * Update mxs-dma device tree binding doc
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

Add dtsi for imx6q and imx6dl with non-common blocks moved into there.
Major differences between imx6dl and imx6q:

 * Dual vs. Quad cores
 * single vs. dual IPU
 * 128 vs. 256 KB OCRAM
 * imx6q: ECSPI5, OpenVG (GC355), SATA
 * imx6dl: I2C4, PXP, EPDC, LCDIF
 * iomuxc/pads definition
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi
file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition
of imx6dl support.

Another member of i.MX6 series i.MX6 SoloLite is different enough
from the other two, so it will stand as a separate dtsi.  That's why
we rename to imx6qdl.dtsi not imx6.dtsi.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

For ANATOP LDOs, vddcpu, vddsoc and vddpu
have step time settings in the misc2 register, need
to add necessary step time info for these three LDOs,
then regulator driver can add necessary delay based on
these settings.

offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc

field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Update operating-points per hardware document and add support for
1 GHz and 1.2 GHz frequencies.

400 MHz, 800 MHz and 1 GHz should be supported by all i.MX6Q chips,
while 1.2 GHz support needs to know from OTP fuse bit.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>