1. 03 10月, 2020 1 次提交
  2. 27 9月, 2020 4 次提交
  3. 19 9月, 2020 3 次提交
  4. 24 7月, 2020 1 次提交
    • V
      net: dsa: stop overriding master's ndo_get_phys_port_name · 5df5661a
      Vladimir Oltean 提交于
      The purpose of this override is to give the user an indication of what
      the number of the CPU port is (in DSA, the CPU port is a hardware
      implementation detail and not a network interface capable of traffic).
      
      However, it has always failed (by design) at providing this information
      to the user in a reliable fashion.
      
      Prior to commit 3369afba ("net: Call into DSA netdevice_ops
      wrappers"), the behavior was to only override this callback if it was
      not provided by the DSA master.
      
      That was its first failure: if the DSA master itself was a DSA port or a
      switchdev, then the user would not see the number of the CPU port in
      /sys/class/net/eth0/phys_port_name, but the number of the DSA master
      port within its respective physical switch.
      
      But that was actually ok in a way. The commit mentioned above changed
      that behavior, and now overrides the master's ndo_get_phys_port_name
      unconditionally. That comes with problems of its own, which are worse in
      a way.
      
      The idea is that it's typical for switchdev users to have udev rules for
      consistent interface naming. These are based, among other things, on
      the phys_port_name attribute. If we let the DSA switch at the bottom
      to start randomly overriding ndo_get_phys_port_name with its own CPU
      port, we basically lose any predictability in interface naming, or even
      uniqueness, for that matter.
      
      So, there are reasons to let DSA override the master's callback (to
      provide a consistent interface, a number which has a clear meaning and
      must not be interpreted according to context), and there are reasons to
      not let DSA override it (it breaks udev matching for the DSA master).
      
      But, there is an alternative method for users to retrieve the number of
      the CPU port of each DSA switch in the system:
      
        $ devlink port
        pci/0000:00:00.5/0: type eth netdev swp0 flavour physical port 0
        pci/0000:00:00.5/2: type eth netdev swp2 flavour physical port 2
        pci/0000:00:00.5/4: type notset flavour cpu port 4
        spi/spi2.0/0: type eth netdev sw0p0 flavour physical port 0
        spi/spi2.0/1: type eth netdev sw0p1 flavour physical port 1
        spi/spi2.0/2: type eth netdev sw0p2 flavour physical port 2
        spi/spi2.0/4: type notset flavour cpu port 4
        spi/spi2.1/0: type eth netdev sw1p0 flavour physical port 0
        spi/spi2.1/1: type eth netdev sw1p1 flavour physical port 1
        spi/spi2.1/2: type eth netdev sw1p2 flavour physical port 2
        spi/spi2.1/3: type eth netdev sw1p3 flavour physical port 3
        spi/spi2.1/4: type notset flavour cpu port 4
      
      So remove this duplicated, unreliable and troublesome method. From this
      patch on, the phys_port_name attribute of the DSA master will only
      contain information about itself (if at all). If the users need reliable
      information about the CPU port they're probably using devlink anyway.
      Signed-off-by: NVladimir Oltean <olteanv@gmail.com>
      Acked-by: Nflorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5df5661a
  5. 21 7月, 2020 2 次提交
  6. 16 7月, 2020 1 次提交
  7. 09 7月, 2020 1 次提交
    • L
      net: dsa: tag_rtl4_a: Implement Realtek 4 byte A tag · efd7fe68
      Linus Walleij 提交于
      This implements the known parts of the Realtek 4 byte
      tag protocol version 0xA, as found in the RTL8366RB
      DSA switch.
      
      It is designated as protocol version 0xA as a
      different Realtek 4 byte tag format with protocol
      version 0x9 is known to exist in the Realtek RTL8306
      chips.
      
      The tag and switch chip lacks public documentation, so
      the tag format has been reverse-engineered from
      packet dumps. As only ingress traffic has been available
      for analysis an egress tag has not been possible to
      develop (even using educated guesses about bit fields)
      so this is as far as it gets. It is not known if the
      switch even supports egress tagging.
      
      Excessive attempts to figure out the egress tag format
      was made. When nothing else worked, I just tried all bit
      combinations with 0xannp where a is protocol and p is
      port. I looped through all values several times trying
      to get a response from ping, without any positive
      result.
      
      Using just these ingress tags however, the switch
      functionality is vastly improved and the packets find
      their way into the destination port without any
      tricky VLAN configuration. On the D-Link DIR-685 the
      LAN ports now come up and respond to ping without
      any command line configuration so this is a real
      improvement for users.
      
      Egress packets need to be restricted to the proper
      target ports using VLAN, which the RTL8366RB DSA
      switch driver already sets up.
      
      Cc: DENG Qingfang <dqfext@gmail.com>
      Cc: Mauri Sandberg <sandberg@mailfence.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      efd7fe68
  8. 30 6月, 2020 1 次提交
  9. 13 5月, 2020 1 次提交
    • R
      net: dsa: provide an option for drivers to always receive bridge VLANs · 54a0ed0d
      Russell King 提交于
      DSA assumes that a bridge which has vlan filtering disabled is not
      vlan aware, and ignores all vlan configuration. However, the kernel
      software bridge code allows configuration in this state.
      
      This causes the kernel's idea of the bridge vlan state and the
      hardware state to disagree, so "bridge vlan show" indicates a correct
      configuration but the hardware lacks all configuration. Even worse,
      enabling vlan filtering on a DSA bridge immediately blocks all traffic
      which, given the output of "bridge vlan show", is very confusing.
      
      Provide an option that drivers can set to indicate they want to receive
      vlan configuration even when vlan filtering is disabled. At the very
      least, this is safe for Marvell DSA bridges, which do not look up
      ingress traffic in the VTU if the port is in 8021Q disabled state. It is
      also safe for the Ocelot switch family. Whether this change is suitable
      for all DSA bridges is not known.
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      54a0ed0d
  10. 11 5月, 2020 3 次提交
    • V
      net: dsa: introduce a dsa_switch_find function · 3b7bc1f0
      Vladimir Oltean 提交于
      Somewhat similar to dsa_tree_find, dsa_switch_find returns a dsa_switch
      structure pointer by searching for its tree index and switch index (the
      parameters from dsa,member). To be used, for example, by drivers who
      implement .crosschip_bridge_join and need a reference to the other
      switch indicated to by the tree_index and sw_index arguments.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      3b7bc1f0
    • V
      net: dsa: permit cross-chip bridging between all trees in the system · f66a6a69
      Vladimir Oltean 提交于
      One way of utilizing DSA is by cascading switches which do not all have
      compatible taggers. Consider the following real-life topology:
      
            +---------------------------------------------------------------+
            | LS1028A                                                       |
            |               +------------------------------+                |
            |               |      DSA master for Felix    |                |
            |               |(internal ENETC port 2: eno2))|                |
            |  +------------+------------------------------+-------------+  |
            |  | Felix embedded L2 switch                                |  |
            |  |                                                         |  |
            |  | +--------------+   +--------------+   +--------------+  |  |
            |  | |DSA master for|   |DSA master for|   |DSA master for|  |  |
            |  | |  SJA1105 1   |   |  SJA1105 2   |   |  SJA1105 3   |  |  |
            |  | |(Felix port 1)|   |(Felix port 2)|   |(Felix port 3)|  |  |
            +--+-+--------------+---+--------------+---+--------------+--+--+
      
      +-----------------------+ +-----------------------+ +-----------------------+
      |   SJA1105 switch 1    | |   SJA1105 switch 2    | |   SJA1105 switch 3    |
      +-----+-----+-----+-----+ +-----+-----+-----+-----+ +-----+-----+-----+-----+
      |sw1p0|sw1p1|sw1p2|sw1p3| |sw2p0|sw2p1|sw2p2|sw2p3| |sw3p0|sw3p1|sw3p2|sw3p3|
      +-----+-----+-----+-----+ +-----+-----+-----+-----+ +-----+-----+-----+-----+
      
      The above can be described in the device tree as follows (obviously not
      complete):
      
      mscc_felix {
      	dsa,member = <0 0>;
      	ports {
      		port@4 {
      			ethernet = <&enetc_port2>;
      		};
      	};
      };
      
      sja1105_switch1 {
      	dsa,member = <1 1>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port1>;
      		};
      	};
      };
      
      sja1105_switch2 {
      	dsa,member = <2 2>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port2>;
      		};
      	};
      };
      
      sja1105_switch3 {
      	dsa,member = <3 3>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port3>;
      		};
      	};
      };
      
      Basically we instantiate one DSA switch tree for every hardware switch
      in the system, but we still give them globally unique switch IDs (will
      come back to that later). Having 3 disjoint switch trees makes the
      tagger drivers "just work", because net devices are registered for the
      3 Felix DSA master ports, and they are also DSA slave ports to the ENETC
      port. So packets received on the ENETC port are stripped of their
      stacked DSA tags one by one.
      
      Currently, hardware bridging between ports on the same sja1105 chip is
      possible, but switching between sja1105 ports on different chips is
      handled by the software bridge. This is fine, but we can do better.
      
      In fact, the dsa_8021q tag used by sja1105 is compatible with cascading.
      In other words, a sja1105 switch can correctly parse and route a packet
      containing a dsa_8021q tag. So if we could enable hardware bridging on
      the Felix DSA master ports, cross-chip bridging could be completely
      offloaded.
      
      Such as system would be used as follows:
      
      ip link add dev br0 type bridge && ip link set dev br0 up
      for port in sw0p0 sw0p1 sw0p2 sw0p3 \
      	    sw1p0 sw1p1 sw1p2 sw1p3 \
      	    sw2p0 sw2p1 sw2p2 sw2p3; do
      	ip link set dev $port master br0
      done
      
      The above makes switching between ports on the same row be performed in
      hardware, and between ports on different rows in software. Now assume
      the Felix switch ports are called swp0, swp1, swp2. By running the
      following extra commands:
      
      ip link add dev br1 type bridge && ip link set dev br1 up
      for port in swp0 swp1 swp2; do
      	ip link set dev $port master br1
      done
      
      the CPU no longer sees packets which traverse sja1105 switch boundaries
      and can be forwarded directly by Felix. The br1 bridge would not be used
      for any sort of traffic termination.
      
      For this to work, we need to give drivers an opportunity to listen for
      bridging events on DSA trees other than their own, and pass that other
      tree index as argument. I have made the assumption, for the moment, that
      the other existing DSA notifiers don't need to be broadcast to other
      trees. That assumption might turn out to be incorrect. But in the
      meantime, introduce a dsa_broadcast function, similar in purpose to
      dsa_port_notify, which is used only by the bridging notifiers.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      f66a6a69
    • V
      net: bridge: allow enslaving some DSA master network devices · 9eb8eff0
      Vladimir Oltean 提交于
      Commit 8db0a2ee ("net: bridge: reject DSA-enabled master netdevices
      as bridge members") added a special check in br_if.c in order to check
      for a DSA master network device with a tagging protocol configured. This
      was done because back then, such devices, once enslaved in a bridge
      would become inoperative and would not pass DSA tagged traffic anymore
      due to br_handle_frame returning RX_HANDLER_CONSUMED.
      
      But right now we have valid use cases which do require bridging of DSA
      masters. One such example is when the DSA master ports are DSA switch
      ports themselves (in a disjoint tree setup). This should be completely
      equivalent, functionally speaking, from having multiple DSA switches
      hanging off of the ports of a switchdev driver. So we should allow the
      enslaving of DSA tagged master network devices.
      
      Instead of the regular br_handle_frame(), install a new function
      br_handle_frame_dummy() on these DSA masters, which returns
      RX_HANDLER_PASS in order to call into the DSA specific tagging protocol
      handlers, and lift the restriction from br_add_if.
      Suggested-by: NNikolay Aleksandrov <nikolay@cumulusnetworks.com>
      Suggested-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Acked-by: NNikolay Aleksandrov <nikolay@cumulusnetworks.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      9eb8eff0
  11. 08 5月, 2020 1 次提交
    • V
      net: dsa: introduce a dsa_port_from_netdev public helper · e1eea811
      Vladimir Oltean 提交于
      As its implementation shows, this is synonimous with calling
      dsa_slave_dev_check followed by dsa_slave_to_port, so it is quite simple
      already and provides functionality which is already there.
      
      However there is now a need for these functions outside dsa_priv.h, for
      example in drivers that perform mirroring and redirection through
      tc-flower offloads (they are given raw access to the flow_cls_offload
      structure), where they need to call this function on act->dev.
      
      But simply exporting dsa_slave_to_port would make it non-inline and
      would result in an extra function call in the hotpath, as can be seen
      for example in sja1105:
      
      Before:
      
      000006dc <sja1105_xmit>:
      {
       6dc:	e92d4ff0 	push	{r4, r5, r6, r7, r8, r9, sl, fp, lr}
       6e0:	e1a04000 	mov	r4, r0
       6e4:	e591958c 	ldr	r9, [r1, #1420]	; 0x58c <- Inline dsa_slave_to_port
       6e8:	e1a05001 	mov	r5, r1
       6ec:	e24dd004 	sub	sp, sp, #4
      	u16 tx_vid = dsa_8021q_tx_vid(dp->ds, dp->index);
       6f0:	e1c901d8 	ldrd	r0, [r9, #24]
       6f4:	ebfffffe 	bl	0 <dsa_8021q_tx_vid>
      			6f4: R_ARM_CALL	dsa_8021q_tx_vid
      	u8 pcp = netdev_txq_to_tc(netdev, queue_mapping);
       6f8:	e1d416b0 	ldrh	r1, [r4, #96]	; 0x60
      	u16 tx_vid = dsa_8021q_tx_vid(dp->ds, dp->index);
       6fc:	e1a08000 	mov	r8, r0
      
      After:
      
      000006e4 <sja1105_xmit>:
      {
       6e4:	e92d4ff0 	push	{r4, r5, r6, r7, r8, r9, sl, fp, lr}
       6e8:	e1a04000 	mov	r4, r0
       6ec:	e24dd004 	sub	sp, sp, #4
      	struct dsa_port *dp = dsa_slave_to_port(netdev);
       6f0:	e1a00001 	mov	r0, r1
      {
       6f4:	e1a05001 	mov	r5, r1
      	struct dsa_port *dp = dsa_slave_to_port(netdev);
       6f8:	ebfffffe 	bl	0 <dsa_slave_to_port>
      			6f8: R_ARM_CALL	dsa_slave_to_port
       6fc:	e1a09000 	mov	r9, r0
      	u16 tx_vid = dsa_8021q_tx_vid(dp->ds, dp->index);
       700:	e1c001d8 	ldrd	r0, [r0, #24]
       704:	ebfffffe 	bl	0 <dsa_8021q_tx_vid>
      			704: R_ARM_CALL	dsa_8021q_tx_vid
      
      Because we want to avoid possible performance regressions, introduce
      this new function which is designed to be public.
      Suggested-by: NVivien Didelot <vivien.didelot@gmail.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NVivien Didelot <vivien.didelot@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e1eea811
  12. 31 3月, 2020 1 次提交
    • V
      net: dsa: add port policers · 34297176
      Vladimir Oltean 提交于
      The approach taken to pass the port policer methods on to drivers is
      pragmatic. It is similar to the port mirroring implementation (in that
      the DSA core does all of the filter block interaction and only passes
      simple operations for the driver to implement) and dissimilar to how
      flow-based policers are going to be implemented (where the driver has
      full control over the flow_cls_offload data structure).
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      34297176
  13. 28 3月, 2020 2 次提交
    • V
      net: dsa: implement auto-normalization of MTU for bridge hardware datapath · bff33f7e
      Vladimir Oltean 提交于
      Many switches don't have an explicit knob for configuring the MTU
      (maximum transmission unit per interface).  Instead, they do the
      length-based packet admission checks on the ingress interface, for
      reasons that are easy to understand (why would you accept a packet in
      the queuing subsystem if you know you're going to drop it anyway).
      
      So it is actually the MRU that these switches permit configuring.
      
      In Linux there only exists the IFLA_MTU netlink attribute and the
      associated dev_set_mtu function. The comments like to play blind and say
      that it's changing the "maximum transfer unit", which is to say that
      there isn't any directionality in the meaning of the MTU word. So that
      is the interpretation that this patch is giving to things: MTU == MRU.
      
      When 2 interfaces having different MTUs are bridged, the bridge driver
      MTU auto-adjustment logic kicks in: what br_mtu_auto_adjust() does is it
      adjusts the MTU of the bridge net device itself (and not that of the
      slave net devices) to the minimum value of all slave interfaces, in
      order for forwarded packets to not exceed the MTU regardless of the
      interface they are received and send on.
      
      The idea behind this behavior, and why the slave MTUs are not adjusted,
      is that normal termination from Linux over the L2 forwarding domain
      should happen over the bridge net device, which _is_ properly limited by
      the minimum MTU. And termination over individual slave devices is
      possible even if those are bridged. But that is not "forwarding", so
      there's no reason to do normalization there, since only a single
      interface sees that packet.
      
      The problem with those switches that can only control the MRU is with
      the offloaded data path, where a packet received on an interface with
      MRU 9000 would still be forwarded to an interface with MRU 1500. And the
      br_mtu_auto_adjust() function does not really help, since the MTU
      configured on the bridge net device is ignored.
      
      In order to enforce the de-facto MTU == MRU rule for these switches, we
      need to do MTU normalization, which means: in order for no packet larger
      than the MTU configured on this port to be sent, then we need to limit
      the MRU on all ports that this packet could possibly come from. AKA
      since we are configuring the MRU via MTU, it means that all ports within
      a bridge forwarding domain should have the same MTU.
      
      And that is exactly what this patch is trying to do.
      
      >From an implementation perspective, we try to follow the intent of the
      user, otherwise there is a risk that we might livelock them (they try to
      change the MTU on an already-bridged interface, but we just keep
      changing it back in an attempt to keep the MTU normalized). So the MTU
      that the bridge is normalized to is either:
      
       - The most recently changed one:
      
         ip link set dev swp0 master br0
         ip link set dev swp1 master br0
         ip link set dev swp0 mtu 1400
      
         This sequence will make swp1 inherit MTU 1400 from swp0.
      
       - The one of the most recently added interface to the bridge:
      
         ip link set dev swp0 master br0
         ip link set dev swp1 mtu 1400
         ip link set dev swp1 master br0
      
         The above sequence will make swp0 inherit MTU 1400 as well.
      Suggested-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bff33f7e
    • V
      net: dsa: configure the MTU for switch ports · bfcb8132
      Vladimir Oltean 提交于
      It is useful be able to configure port policers on a switch to accept
      frames of various sizes:
      
      - Increase the MTU for better throughput from the default of 1500 if it
        is known that there is no 10/100 Mbps device in the network.
      - Decrease the MTU to limit the latency of high-priority frames under
        congestion, or work around various network segments that add extra
        headers to packets which can't be fragmented.
      
      For DSA slave ports, this is mostly a pass-through callback, called
      through the regular ndo ops and at probe time (to ensure consistency
      across all supported switches).
      
      The CPU port is called with an MTU equal to the largest configured MTU
      of the slave ports. The assumption is that the user might want to
      sustain a bidirectional conversation with a partner over any switch
      port.
      
      The DSA master is configured the same as the CPU port, plus the tagger
      overhead. Since the MTU is by definition L2 payload (sans Ethernet
      header), it is up to each individual driver to figure out if it needs to
      do anything special for its frame tags on the CPU port (it shouldn't
      except in special cases). So the MTU does not contain the tagger
      overhead on the CPU port.
      However the MTU of the DSA master, minus the tagger overhead, is used as
      a proxy for the MTU of the CPU port, which does not have a net device.
      This is to avoid uselessly calling the .change_mtu function on the CPU
      port when nothing should change.
      
      So it is safe to assume that the DSA master and the CPU port MTUs are
      apart by exactly the tagger's overhead in bytes.
      
      Some changes were made around dsa_master_set_mtu(), function which was
      now removed, for 2 reasons:
        - dev_set_mtu() already calls dev_validate_mtu(), so it's redundant to
          do the same thing in DSA
        - __dev_set_mtu() returns 0 if ops->ndo_change_mtu is an absent method
      That is to say, there's no need for this function in DSA, we can safely
      call dev_set_mtu() directly, take the rtnl lock when necessary, and just
      propagate whatever errors get reported (since the user probably wants to
      be informed).
      
      Some inspiration (mainly in the MTU DSA notifier) was taken from a
      vaguely similar patch from Murali and Florian, who are credited as
      co-developers down below.
      Co-developed-by: NMurali Krishna Policharla <murali.policharla@broadcom.com>
      Signed-off-by: NMurali Krishna Policharla <murali.policharla@broadcom.com>
      Co-developed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bfcb8132
  14. 04 3月, 2020 1 次提交
  15. 28 2月, 2020 1 次提交
  16. 09 1月, 2020 1 次提交
    • F
      net: dsa: Get information about stacked DSA protocol · 4d776482
      Florian Fainelli 提交于
      It is possible to stack multiple DSA switches in a way that they are not
      part of the tree (disjoint) but the DSA master of a switch is a DSA
      slave of another. When that happens switch drivers may have to know this
      is the case so as to determine whether their tagging protocol has a
      remove chance of working.
      
      This is useful for specific switch drivers such as b53 where devices
      have been known to be stacked in the wild without the Broadcom tag
      protocol supporting that feature. This allows b53 to continue supporting
      those devices by forcing the disabling of Broadcom tags on the outermost
      switches if necessary.
      
      The get_tag_protocol() function is therefore updated to gain an
      additional enum dsa_tag_protocol argument which denotes the current
      tagging protocol used by the DSA master we are attached to, else
      DSA_TAG_PROTO_NONE for the top of the dsa_switch_tree.
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4d776482
  17. 06 1月, 2020 2 次提交
    • V
      net: dsa: Pass pcs_poll flag from driver to PHYLINK · 787cac3f
      Vladimir Oltean 提交于
      The DSA drivers that implement .phylink_mac_link_state should normally
      register an interrupt for the PCS, from which they should call
      phylink_mac_change(). However not all switches implement this, and those
      who don't should set this flag in dsa_switch in the .setup callback, so
      that PHYLINK will poll for a few ms until the in-band AN link timer
      expires and the PCS state settles.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      787cac3f
    • V
      net: dsa: Make deferred_xmit private to sja1105 · a68578c2
      Vladimir Oltean 提交于
      There are 3 things that are wrong with the DSA deferred xmit mechanism:
      
      1. Its introduction has made the DSA hotpath ever so slightly more
         inefficient for everybody, since DSA_SKB_CB(skb)->deferred_xmit needs
         to be initialized to false for every transmitted frame, in order to
         figure out whether the driver requested deferral or not (a very rare
         occasion, rare even for the only driver that does use this mechanism:
         sja1105). That was necessary to avoid kfree_skb from freeing the skb.
      
      2. Because L2 PTP is a link-local protocol like STP, it requires
         management routes and deferred xmit with this switch. But as opposed
         to STP, the deferred work mechanism needs to schedule the packet
         rather quickly for the TX timstamp to be collected in time and sent
         to user space. But there is no provision for controlling the
         scheduling priority of this deferred xmit workqueue. Too bad this is
         a rather specific requirement for a feature that nobody else uses
         (more below).
      
      3. Perhaps most importantly, it makes the DSA core adhere a bit too
         much to the NXP company-wide policy "Innovate Where It Doesn't
         Matter". The sja1105 is probably the only DSA switch that requires
         some frames sent from the CPU to be routed to the slave port via an
         out-of-band configuration (register write) rather than in-band (DSA
         tag). And there are indeed very good reasons to not want to do that:
         if that out-of-band register is at the other end of a slow bus such
         as SPI, then you limit that Ethernet flow's throughput to effectively
         the throughput of the SPI bus. So hardware vendors should definitely
         not be encouraged to design this way. We do _not_ want more
         widespread use of this mechanism.
      
      Luckily we have a solution for each of the 3 issues:
      
      For 1, we can just remove that variable in the skb->cb and counteract
      the effect of kfree_skb with skb_get, much to the same effect. The
      advantage, of course, being that anybody who doesn't use deferred xmit
      doesn't need to do any extra operation in the hotpath.
      
      For 2, we can create a kernel thread for each port's deferred xmit work.
      If the user switch ports are named swp0, swp1, swp2, the kernel threads
      will be named swp0_xmit, swp1_xmit, swp2_xmit (there appears to be a 15
      character length limit on kernel thread names). With this, the user can
      change the scheduling priority with chrt $(pidof swp2_xmit).
      
      For 3, we can actually move the entire implementation to the sja1105
      driver.
      
      So this patch deletes the generic implementation from the DSA core and
      adds a new one, more adequate to the requirements of PTP TX
      timestamping, in sja1105_main.c.
      Suggested-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NVladimir Oltean <olteanv@gmail.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a68578c2
  18. 21 12月, 2019 1 次提交
  19. 16 11月, 2019 1 次提交
    • V
      net: dsa: ocelot: add tagger for Ocelot/Felix switches · 8dce89aa
      Vladimir Oltean 提交于
      While it is entirely possible that this tagger format is in fact more
      generic than just these 2 switch families, I don't have that knowledge.
      The Seville switch in NXP T1040 has a similar frame format, but there
      are enough differences (e.g. DEST field starts at bit 57 instead of 56)
      that calling this file tag_vitesse.c is a bit of a stretch at the
      moment. The frame format has been listed in a comment so that people who
      add support for further Vitesse switches can rework this tagger while
      keeping compatibility with Felix.
      
      The "ocelot" name was chosen instead of "felix" because even the Ocelot
      switch can act as a DSA device when it is used in NPI mode, and the Felix
      tagger format is almost identical. Currently it is only used for the
      Felix switch embedded in the NXP LS1028A chip.
      
      The ABI for this tagger should be considered "not stable" at the moment.
      The DSA tag is always placed before the Ethernet header and therefore,
      we are using the long prefix for RX tags to avoid putting the DSA master
      port in promiscuous mode. Once there will be an API in DSA for drivers
      to request DSA masters to be in promiscuous mode unconditionally, we
      will switch to the "no prefix" extraction frame header, which will save
      16 padding bytes for each RX frame.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8dce89aa
  20. 06 11月, 2019 1 次提交
  21. 01 11月, 2019 3 次提交
  22. 30 10月, 2019 1 次提交
  23. 29 10月, 2019 1 次提交
  24. 23 10月, 2019 5 次提交