1. 12 2月, 2021 1 次提交
    • S
      octeontx2-af: cn10k: Add support for programmable channels · 242da439
      Subbaraya Sundeep 提交于
      NIX uses unique channel numbers to identify the packet sources/sinks
      like CGX,LBK and SDP. The channel numbers assigned to each block are
      hardwired in CN9xxx silicon.
      The fixed channel numbers in CN9xxx are:
      
      0x0 | a << 8 | b            - LBK(0..3)_CH(0..63)
      0x0 | a << 8                - Reserved
      0x700 | a                   - SDP_CH(0..255)
      0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15)
      
      All the channels in the above fixed enumerator(with maximum
      number of blocks) are not required since some chips
      have less number of blocks.
      For CN10K silicon the channel numbers need to be programmed by
      software in each block with the base channel number and range of
      channels. This patch calculates and assigns the channel numbers
      to efficiently distribute the channel number range(0-4095) among
      all the blocks. The assignment is made based on the actual number of
      blocks present and also contiguously leaving no holes.
      The channel numbers remaining after the math are used as new CPT
      replay channels present in CN10K. Also since channel numbers are
      not fixed the transmit channel link number needed by AF consumers
      is calculated by AF and sent along with nix_lf_alloc mailbox response.
      Signed-off-by: NSubbaraya Sundeep <sbhatta@marvell.com>
      Signed-off-by: NGeetha sowjanya <gakula@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      242da439
  2. 18 11月, 2020 6 次提交
  3. 01 11月, 2020 1 次提交
  4. 01 10月, 2020 1 次提交
  5. 30 9月, 2020 1 次提交
    • S
      octeontx2-af: cleanup KPU config data · 42006910
      Stanislaw Kardach 提交于
      Refactor KPU related NPC code gathering all configuration data in a
      structured format and putting it in one place (npc_profile.h).
      This increases readability and makes it easier to extend the profile
      configuration (as opposed to jumping between multiple header and source
      files).
      
      To do this:
      * Gather all KPU profile related data into a single adapter struct.
      * Convert the built-in MKEX definition to a structured one to streamline
        the MKEX loading.
      * Convert LT default register configuration into a structure, keeping
        default protocol settings in same file where identifiers for those
        protocols are defined.
      * Add a single point for KPU profile loading, so that its source may
        change in the future once proper interfaces for loading such config
        are in place.
      Signed-off-by: NStanislaw Kardach <skardach@marvell.com>
      Acked-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      42006910
  6. 12 9月, 2020 1 次提交
  7. 25 8月, 2020 1 次提交
  8. 03 3月, 2020 1 次提交
    • L
      octeontx2-af: Optimize data retrieval from firmware · 4f4eebf2
      Linu Cherian 提交于
      For retrieving info like interface MAC addresses, packet
      parser key extraction config etc currently a command
      is sent to firmware and firmware which periodically polls
      for commands, processes these and returns the info.
      
      This is resulting in interface initialization taking lot
      of time. To optimize this a memory region is shared between
      firmware and this driver, firmware while booting puts
      static info like these into that region for driver to
      read directly without using commands.
      
      With this
      - Logic for retrieving packet parser extraction config
        via commands is removed and repalced with using the
        shared 'fwdata' structure.
      - Now RVU MSIX vector address is also retrieved from this fwdata struct
        instead of from CSR. Otherwise when kexec/kdump crash kernel loads
        CSR will have a IOVA setup by primary kernel which impacts
        RVU PF/VF's interrupts.
      - Also added a mbox handler for PF/VF interfaces to retrieve their MAC
        addresses from AF.
      Signed-off-by: NLinu Cherian <lcherian@marvell.com>
      Signed-off-by: NChristina Jacob <cjacob@marvell.com>
      Signed-off-by: NRakesh Babu <rsaladi2@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4f4eebf2
  9. 15 11月, 2019 5 次提交
    • S
      octeontx2-af: Enable broadcast packet replication · 561e8752
      Sunil Goutham 提交于
      Ingress packet replication support has been added to 96xx B0
      silicon. This patch enables using that feature to replicate
      ingress broadcast packets to PF and it's VFs.
      
      Also fixed below issues
      - VFs can also install NPC MCAM entry to forward broadcast pkts.
        Otherwise, unless PF's interface is UP, VFs will not receive
        bcast packets.
      - NPC MCAM entry is disabled when PF and all it's VFs are down.
      - Few corner cases in installing multicast entry list.
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      561e8752
    • S
      octeontx2-af: Support fixed transmit scheduler topology · 5d9b976d
      Sunil Goutham 提交于
      CN96xx initial silicon doesn't support all features pertaining to
      NIX transmit scheduling and shaping.
      - It supports a fixed topology of 1:1 mapped transmit
        limiters at all levels.
      - Supports DWRR only at SMQ/MDQ and TL1.
      - Doesn't support shaping and coloring.
      
      This patch adds HW capability structure by which each variant
      and skew of silicon can be differentiated by their supported
      features. And adds support for A0 silicon's transmit scheduler
      capabilities or rather limitations.
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5d9b976d
    • N
      octeontx2-af: Clear NPC MCAM entries before update · 8cc89ae9
      Nithin Dabilpuram 提交于
      Writing into NPC MCAM1 and MCAM0 registers are suppressed if
      they happened to form a reserved combination. Hence
      clear and disable MCAM entries before update.
      
      For HRM:
      [CAM(1)]<n>=1, [CAM(0)]<n>=1: Reserved.
      The reserved combination is not allowed. Hardware suppresses any
      write to CAM(0) or CAM(1) that would result in the reserved combination for
      any CAM bit.
      Signed-off-by: NNithin Dabilpuram <ndabilpuram@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8cc89ae9
    • H
      octeontx2-af: Update NPC KPU packet parsing profile · 922584f6
      Hao Zheng 提交于
      Updated NPC KPU packet parsing profile with support for following
      
      - Fragmentation support for IPv4 IPv6 outer header
      - NIX instruction header support
      - QinQ with TPID of 0x8100 as non inner most vlan tag, as legacy
        network equipments still generate QinQ packets with this configuration.
      - To better support RSS for tunnelled packets, udp based tunnel
        protocols such as vxlan, vxlan-gpe, geneve and gtpu are now
        captured into a separate layer E. Consequently, the inner
        packet headers are pushed one layer down to LF, LG, and LH
        accordingly.
      - Support for rfc7510 mpls in udp. Up to 4 MPLS labels can be parsed
        and captured in one layer LE.
      - Parser support for DSA, extended DSA and eDSA tags right after
        ethernet header by Marvell SOHO and Falcon switches. For extended
        DSA and eDSA tags, a special PKIND of 62 is used, as these tags don't
        contain a tpid field.
      - Higig2 protocol header parsing support, added a NPC_LT_LA_HIGIG2_ETHER
        for a combined header of HIGIG2 and Ethernet.  Add a
        NPC_LT_LA_IH_NIX_HIGIG2_ETHER for a combined header of nix_ih,
        HIGIG2 and Ethernet on egress side. Also added 2 upper flags in LA to
        indicate the presence of nix_ih and HIGIG2.
      
      Other changes include
      - IPv4.TTL==0 IPv6.HLIM==0 check
      - Per RFC 1858, mark fragment offset == 1 as error
      - TCP invalid flags check
      - Separate error codes for outer and inner IPv4 checksum errors.
      - Fix a parser error when KPU parses incoming IPSec ESP and AH packets
      - NPC vtag capture/strip hardware expect tag pointer to point to
        tpid/ethertype instead of tci. So move lb_ptr to point to tpid/ethertype.
      - Fix npc parser error when parsing udp packets that don't have any payload.
      - For a single MCAM entry to match on packets with one or stacked vlan tags
        combine NPC_LT_LB_STAG and NPC_LT_LB_QINQ to NPC_LT_LB_STAG_QINQ.
      - NVGRE to have a separate ltype LD_NVGRE instead of combined with LD_GRE.
      - Reserve top LD/LTYPEs to support custom KPU profile fields.
      Signed-off-by: NHao Zheng <haoz@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      922584f6
    • S
      octeontx2-af: Add NPC MCAM entry allocation status to debugfs · e07fb507
      Sunil Goutham 提交于
      Added support to display current NPC MCAM entries and counter's allocation
      status ín debugfs.
      
      cat /sys/kernel/debug/octeontx2/npc/mcam_info' will dump following info
      - MCAM Rx and Tx keysize
      - Total MCAM entries and counters
      - Current available count
      - Count of number of MCAM entries and counters allocated
        by a RVU PF/VF device.
      
      Also, one NPC MCAM counter (last one) is reserved and mapped to
      NPC RX_INTF's MISS_ACTION to count dropped packets due to no MCAM
      entry match. This pkt drop counter can be checked via debugfs.
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e07fb507
  10. 04 12月, 2018 4 次提交
  11. 20 11月, 2018 11 次提交
  12. 23 10月, 2018 7 次提交