1. 27 3月, 2012 1 次提交
  2. 26 3月, 2012 1 次提交
  3. 24 3月, 2012 6 次提交
  4. 07 3月, 2012 1 次提交
  5. 03 3月, 2012 3 次提交
    • K
      ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/ · 84c028b9
      Kukjin Kim 提交于
      This patch moves S3C2443 stuff into mach-s3c24xx/ directory
      so that we can merge the s3c24 series' directories to the
      just one mach-s3c24xx/ directory.
      
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      84c028b9
    • K
      ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/ · 85fd6d63
      Kukjin Kim 提交于
      This patch moves S3C2410 stuff into mach-s3c24xx/ directory
      so that we can merge the s3c24 series' directories to the
      just one mach-s3c24xx/ directory.
      
      And this patch is including following.
      - re-ordered alphabetically by option text at Kconfig and Makefile
      - removed unused option, MACH_N35
      - fixed duplcated option name, S3C2410_DMA to S3C24XX_DMA which is
        in plat-s3c24xx/
      
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      85fd6d63
    • K
      ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX · b130d5c2
      Kukjin Kim 提交于
      This patch changes the ARCH name to "ARCH_S3C24XX" for Samsung
      S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443,
      and S3C2450 SoCs so that we can merge the mach-xxx directories
      and plat-s3c24xx dir. to just one mach-s3c24xx for them.
      
      I think this should be sent to upstream via samsung tree because
      this touches many samsung stuff.
      
      Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
      Cc: Richard Purdie <rpurdie@rpsys.net>
      Cc: Chris Ball <cjb@laptop.org>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Alessandro Zummo <a.zummo@towertech.it>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Greg Kroah-Hartman <gregkh@suse.de>
      [for the gadget part:]
      Acked-by: NFelipe Balbi <balbi@ti.com>
      [for the framebuffer (video) part:]
      Acked-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
      [For the watchdog-part:]
      Acked-by: NWim Van Sebroeck <wim@iguana.be>
      Cc: Sangbeom Kim <sbkim73@samsung.com>
      Cc: Liam Girdwood <lrg@ti.com>
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      b130d5c2
  6. 01 3月, 2012 2 次提交
  7. 29 2月, 2012 1 次提交
  8. 28 2月, 2012 2 次提交
  9. 27 2月, 2012 1 次提交
  10. 22 2月, 2012 1 次提交
  11. 10 2月, 2012 1 次提交
  12. 03 2月, 2012 4 次提交
  13. 31 1月, 2012 1 次提交
  14. 26 1月, 2012 1 次提交
    • R
      irq: make SPARSE_IRQ an optionally hidden option · 2ed86b16
      Rob Herring 提交于
      On ARM, we don't want SPARSE_IRQ to be a user visible option. Make
      SPARSE_IRQ visible based on MAY_HAVE_SPARSE_IRQ instead of depending
      on HAVE_SPARSE_IRQ.
      
      With this, SPARSE_IRQ is not visible on C6X and ARM.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-c6x-dev@linux-c6x.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-sh@vger.kernel.org
      2ed86b16
  15. 23 1月, 2012 1 次提交
    • W
      ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs · a092f2b1
      Will Deacon 提交于
      To ensure correct alignment of cacheline-aligned data, the maximum
      cacheline size needs to be known at compile time.
      
      Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
      that there will be future ARMv7 implementations with the same line size)
      then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
      size. For CPUs with smaller caches, this will result in some harmless
      padding but will help with single zImage work and avoid hitting subtle
      bugs with misaligned data structures.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a092f2b1
  16. 19 1月, 2012 1 次提交
  17. 11 1月, 2012 1 次提交
  18. 05 1月, 2012 1 次提交
  19. 28 12月, 2011 2 次提交
  20. 24 12月, 2011 5 次提交
  21. 19 12月, 2011 3 次提交