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  1. 08 1月, 2019 2 次提交
  3. 11 12月, 2018 1 次提交
  5. 14 11月, 2018 1 次提交
  7. 07 11月, 2018 2 次提交
  9. 05 11月, 2018 1 次提交
  11. 21 10月, 2018 1 次提交
  13. 19 10月, 2018 1 次提交
    • L
      spi: spi-mem: add stm32 qspi controller · c530cd1d
      由 Ludovic Barre 提交于 
      The qspi controller is a specialized communication interface
targeting single, dual or quad SPI Flash memories (NOR/NAND).

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory

tested on:
-NOR: mx66l51235l
-NAND: MT29F2G01ABAGD
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      c530cd1d
  15. 11 10月, 2018 2 次提交
  17. 28 9月, 2018 1 次提交
  19. 10 9月, 2018 1 次提交
  21. 29 8月, 2018 1 次提交
  23. 01 8月, 2018 1 次提交
  25. 31 5月, 2018 1 次提交
  27. 11 5月, 2018 1 次提交
  29. 10 5月, 2018 1 次提交
  31. 18 4月, 2018 1 次提交
  33. 26 3月, 2018 2 次提交
  35. 12 2月, 2018 1 次提交
  37. 03 11月, 2017 1 次提交
  39. 06 10月, 2017 1 次提交
    • A
      spi: spreadtrum adi: add hwspinlock dependency · e83f3742
      由 Arnd Bergmann 提交于 
      With CONFIG_HWSPINLOCK=m, the new driver fails to link as a built-in driver:

drivers/spi/spi-sprd-adi.o: In function `sprd_adi_remove':
spi-sprd-adi.c:(.text+0x18): undefined reference to `hwspin_lock_free'
drivers/spi/spi-sprd-adi.o: In function `sprd_adi_probe':
spi-sprd-adi.c:(.text+0xfc): undefined reference to `of_hwspin_lock_get_id'
spi-sprd-adi.c:(.text+0x108): undefined reference to `hwspin_lock_request_specific'
spi-sprd-adi.c:(.text+0x268): undefined reference to `hwspin_lock_free'

This adds a hard Kconfig dependency on HWSPINLOCK for the !COMPILE_TEST
case, and allows compile-testing with HWSPINLOCK completely disabled,
which will then rely on the existing stub API.

Fixes: 7e2903cb ("spi: Add ADI driver for Spreadtrum platform")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
      e83f3742
  41. 20 9月, 2017 1 次提交
  43. 19 9月, 2017 1 次提交
  45. 16 8月, 2017 1 次提交
    • L
      spi: altera: Switch to SPI core transfer queue management · e19b63cd
      由 Lars-Peter Clausen 提交于 
      The Altera SPI driver currently uses the spi-bitbang infrastructure for
transfer queue management, but non of the bitbang functionality itself.
This is because when the driver was written this was the only way to not
have to do queue management in the driver itself.

Nowadays transfer queue management is available from the SPI driver core
itself and using the bitbang infrastructure just adds an additional level
of indirection.

Switch the driver over to using the core queue management directly.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
      e19b63cd
  47. 07 8月, 2017 1 次提交
    • A
      spi: fix building SPI_PXA on MMP · 128345b1
      由 Arnd Bergmann 提交于 
      When the audio driver selects CONFIG_PXA_SSP on ARCH_MMP as a
loadable module, and the PXA SPI driver is built-in, we get
a link error in the SPI driver:

drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_remove':
spi-pxa2xx.c:(.text+0x5f0): undefined reference to `pxa_ssp_free'
drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_probe':
spi-pxa2xx.c:(.text+0xeac): undefined reference to `pxa_ssp_request'
spi-pxa2xx.c:(.text+0x1468): undefined reference to `pxa_ssp_free'
spi-pxa2xx.c:(.text+0x15bc): undefined reference to `pxa_ssp_free'

The problem is that the PXA SPI driver only uses 'select SSP'
specifically when building it for PXA, but we can also build it
for PCI, which is meant for Intel x86 SoCs that use the same SPI
block. When the sound driver forces the SSP to be a loadable
module, the IS_ENABLED() check in include/linux/pxa2xx_ssp.h
triggers but the spi driver can't reference the exported symbols.

I had a different approach before, making the PCI case depend
on X86, which fixed the problem by avoiding the MMP case.

This goes a different route, making the driver select PXA_SSP
also on MMP, which has an SSP that none of the boards in mainline
Linux use for SPI. There is no harm in always enabling the build
on MMP (PCI or not PCI), so I do that too, to document that this
hardware is actually available on MMP.

Link: https://patchwork.kernel.org/patch/8879921/Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
      128345b1
  49. 21 6月, 2017 1 次提交
  51. 26 5月, 2017 3 次提交
  53. 25 5月, 2017 1 次提交
  55. 14 5月, 2017 1 次提交
  57. 14 3月, 2017 1 次提交
  59. 20 2月, 2017 1 次提交
  61. 15 2月, 2017 1 次提交
    • H
      spi: lantiq-ssc: add support for Lantiq SSC SPI controller · 17f84b79
      由 Hauke Mehrtens 提交于 
      This driver supports the Lantiq SSC SPI controller in master
mode. This controller is found on Intel (former Lantiq) SoCs like
the Danube, Falcon, xRX200, xRX300.

The hardware uses two hardware FIFOs one for received and one for
transferred bytes. When the driver writes data into the transmit FIFO
the complete word is taken from the FIFO into a shift register. The
data from this shift register is then written to the wire. This driver
uses the interrupts signaling the status of the FIFOs and not the shift
register. It is also possible to use the interrupts for the shift
register, but they will send a signal after every word. When using the
interrupts for the shift register we get a signal when the last word is
written into the shift register and not when it is written to the wire.
After all FIFOs are empty the driver busy waits till the hardware is
not busy any more and returns the transfer status.
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
      17f84b79
  63. 10 1月, 2017 1 次提交
  65. 01 1月, 2017 1 次提交
  67. 14 12月, 2016 1 次提交