Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.

We do not need this from gfx10 onwards because >=gfx10 has
asynchronous compute tunneling to replace wave limit requirement.
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that register simultaneously.
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch consist of below related changes:

1 Rename ring->priority to ring->hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring->priority_mutex as ring priority remains unchanged
  after initialization.
4 Remove unused ring->num_jobs.

v3: remove ring->num_jobs.
v2: remove ring->priority_mutex.

Fixes: 33abcb1f ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: NNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The dm struct is only being used if DCN config is defined and this
causes a unused variable warning if DCN option is not set.

[How]
Remove the compile flag so the variable is used (there also seems to be
a duplicate guard due to a bad rebase) so remove the outer guard to fix
the warning.

Fixes this warning
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function 'dm_set_vblank':
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5380:33: warning: unused variable 'dm' [-Wunused-variable]

Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3")
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit 4c3a3292.

Bhawan's fix is better (less ifdefs), so revert this and apply Bhawan's.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

After all users of the 'dm' warnings got hidden in an #ifdef,
the compiler started warning about it being unused:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable]

Add another such #ifdef.

Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org

Add matrix_bits and coeffs_precision to ccorr private data:
- matrix bits of mt8183 is 10
- matrix bits of mt8192 is 11
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Fix setting to follow hardware datasheet. The original error setting
affects mt8192 display.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

ccorr ctm matrix bits will be different in mt8192.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Enable dither function to improve the display quality.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
ovl will hang up when more than 1 layer enabled.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

1. Add ovl private data
2. Add rdma private data
3. Add gamma privte data
4. Add main and external path module for crtc create
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Not all SoC has dither function in gamma module.
Add private data to control this function setting.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mt8183 gamma module will different with mt8173,
so separate gamma for adding private data.
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Current implementation of mtk_dither_set() cast dev data to
struct mtk_ddp_comp_dev. But other devices with different dev data
would also call this function.

Separate necessary parameters out so other device components (dither,
gamma) can call this function.
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>

Moving mutex resource management from client driver to  mutex driver
could prevent client drivers negotiating for resource management.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

mtk mutex is used by both drm and mdp driver, so change disp/ddp term to
mutex to show that it's a common driver for drm and mdp.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c
has only mtk mutex function, so rename it to match the function in it.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Those file includings are useless, so remove them.
Signed-off-by: NCK Hu <ck.hu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Get the fifo size from device tree
because each rdma in the same SoC may have different fifo size
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

The orginal setting is not correct, fix it to follow hardware data sheet.
If keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.

Fixes: 0664d139 ("drm/mediatek: Add AAL engine basic function")
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

Similar to commit a9d9fea7
("drm/mediatek: mtk_dsi: Create connector for bridges"):

Use the drm_bridge_connector helper to create a connector for pipelines
that use drm_bridge. This allows splitting connector operations across
multiple bridges when necessary, instead of having the last bridge in
the chain creating the connector and handling all connector operations
internally.
Signed-off-by: NHsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

It's possible that state->base.fb is null. Add a check before access its
format.

Fixes: b6b1bb98 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha")
Signed-off-by: NYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: NChun-Kuang Hu <chunkuang.hu@kernel.org>

If the user passes a "level" value which is higher than 31 then that
leads to shift wrapping.  The undefined behavior will lead to a
syzkaller stack dump.

Fixes: 5632708f ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)")
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Remove unneeded variable: "pattern".
Signed-off-by: NBernard Zhao <bernard@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check GFX DPM and PG bit before enable GFXOFF on Vangogh
smu post init.
Signed-off-by: NJinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:
- Better handling of dummy p-state table
- Workaround for some legacy DP-VGA dongles
- Add Freesync HDMI support to DMCU
- Enable "trigger_hotplug" debugfs on all outputs
- fix initial bounding box values for dcn3.02
- implement support for DID2.0 dsc passthrough
- fix calculation for the pwl backlight curve
- Fix multiple memory leaks
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Overlay won't move to a new positon if viewport size is smaller than
what can be handled. It'd either disappear or stay at the old
position. This condition is for example hit if overlay is moved too
much outside of left or top edge of the screen, but it applies to
any non-cursor plane type.

[how]
Reject this contidion at validation time. This gives the calling
level a chance to handle this gracefully and avoid inconsistent
behaivor.
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some scenarios where we use a UCLK frequency in between dummy p-state table
entries result in a p-state hang, due to the table not having a close
enough match, so the default DPM0 latency is used, which can be too long to
support dummy p-state switching in these scenarios.

[How]
 - old: match if current freq is within +- margin of table entry
 - new: find largest table entry that is lower than current freq + margin
   - lower than DPM0 will still use DPM0
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA
dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and
this leads to the maximum resolution 1920*1080 cannot be obtained from EDID.

[How]
Provide a workaround for some legacy DP-VGA dongles with a longer aux delay.
Signed-off-by: NTaimur Hassan <syed.hassan@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
An old dc_sink state is causing a memory leak because it is missing a
dc_sink_release before a new dc_sink is assigned back to
aconnector->dc_sink.

[how]
Decrement the dc_sink refcount before reassigning it to a new dc_sink.
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
drm_atomic_commit was changed so that the caller must free their
drm_atomic_state reference on successes.

[how]
Add drm_atomic_commit_put after drm_atomic_commit call in
dm_force_atomic_commit.
Signed-off-by: NVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: NRoman Li <Roman.Li@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Remove force_ignore_link_settings debug option as it is no longer used.
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Adding support for Freesync HDMI to DC and DMCU

[How]
Create DC interface and implementation on top of DMCU to support
parsing CEA blocks in DMCU.
Signed-off-by: NStylon Wang <stylon.wang@amd.com>
Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Per-connector debugfs entry "trigger_hotplug" is available on DP/eDP only.
New IGT tests need this entry to test other outputs.

[How]
Enable this debugfs entry on all types of connectors
Signed-off-by: NStylon Wang <stylon.wang@amd.com>
Reviewed-by: NMikita Lipski <Mikita.Lipski@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The conditions for whether we used cached vs non-cached inbox1 depend
on a version check that mismatches what the shared helpers in dmub20
implement.

[How]
Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Initial bounding box values are updated in dcn30_update_bw_bounding_box
 but they use dcn3_0_soc and dcn3_0_ip instead of dcn3_02_soc and
 dcn3_02_ip

[How]
Add dcn302_update_bw_bounding_box and
 dcn302_get_optimal_dcfclk_fclk_for_uclk so it uses
 dcn3_02_soc and dcn3_02_ip.
Use sr_exit_time_us, sr_enter_plus_exit_time_us,
 from dcn30 on dcn302 to fix flicker on eDP.
 Also use dram_clock_change_latency_us from dcn30.
Signed-off-by: NSamson Tam <Samson.Tam@amd.com>
Reviewed-by: NJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some panels contain active converters (e.g. DP to MIPI) which only support
restricted DSC configurations.  DID2.0 adds support for such displays to
explicitly define per timing BPP restrictions on DSC.  Ignoring these
restrictions leads to blackscreen.

[How]
Add parsing in DID2.0 parser to get this bpp info.
Add support in DSC module to constraint target bpp based
on this info.
Signed-off-by: NJun Lei <jun.lei@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NAnson Jacob <Anson.Jacob@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>