All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Select ARCH_WANT_OPTIONAL_GPIOLIB from BRCMSTB to allow GPIOLIB and
GPIO_BRCMSTB to be enabled.
Signed-off-by: NGregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Select CONFIG_MTD_NAND_BRCMNAND for all iProc SoCs
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We need to unlock and unmap some resourses before returning.

Fixes: 3f2a43c9 ('ARM: BCM63xx: Add secondary CPU PMB initialization sequence')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add support for booting the secondary CPU on BCM63138, this involves:

- locating the bootlut to write the reset vector
- powering up the second CPU when we need to using the DT-supplied PMB
  references
- disabling VFP when enabled such that we can keep having SMP
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The sequence to initialize a secondary CPU using the BCM63138 PMB is
extremely specific and represents much more code than any other on-chip
peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we
keep that code local and utilize Device Tree to lookup all the resources
we need from the CPU device tree node.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Broadcom ARM devices seem to generate some fault once per boot. We
already have an ignoring handler for BCM4707/BCM4708, but BCM4709
generates different code.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Since the WDT is what's used to drive restart and power off, it makes
more sense to keep it there, where the regs are already mapped and
definitions for them provided.  Note that this means you may need to
add CONFIG_BCM2835_WDT to retain functionality of your kernel.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This is the default function that gets called if the hook is NULL.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The only thing we were using this 16MB mapping of IO peripherals for
was the uart's early debug mapping.  If we just drop the map_io hook,
the kernel will call debug_ll_io_init() for us, which maps the single
page needed for the device.
Signed-off-by: NEric Anholt <eric@anholt.net>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The const declaration for char* is actually duplicated, however
the array of strings is currently not constant. However, typically
the dt_compat array is declared as const char *const. Follow
that convention and also add the __initconst macro for constant
initialization data.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NScott Branden <sbranden@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Tested-by: NRay Jui <rjui@broadcom.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The definition

	static const char *axxia_dt_match[] __initconst = {
		...

defines a changable array of constant strings. That is you must not do:

	*axxia_dt_match[0] = 'k';

but

	axxia_dt_match[0] = "different string";

is fine. So the annotation __initconst is wrong and yields a compiler
error when other really const variables are added with __initconst.

As the struct machine_desc member dt_compat is declared as

	const char *const *dt_compat;

making the arrays const is the better alternative over changing all
annotations to __initdata.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

A recent cleanup rearranged the Kconfig file for mach-bcm and
accidentally dropped the dependency on ARCH_MULTI_V7, which
makes it possible to now build the two mobile SoC platforms
on an ARMv6-only kernel, resulting in a log of Kconfig
warnings like

warning: ARCH_BCM_MOBILE selects ARM_ERRATA_775420 which has unmet direct dependencies (CPU_V7)

and which of course cannot work on any machine.

This puts back the dependencies as before.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 64e74aa7 ("ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig")
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NScott Branden <sbranden@broadcom.com>

The automatic CPU power state machine for B15 CPUs does not work
reliably as-is. This patch implements a manual sequence in software to
replace it.

This was tested successfully with over 10,000 hotplug cycles of
something like this:

  echo 0 > /sys/devices/system/cpu/cpu1/online
  echo 1 > /sys/devices/system/cpu/cpu1/online

whereas the existing sequence often locks up after a few hundred cycles.

Fixes: 62639c2f ("ARM: brcmstb: reintroduce SMP support")
Acked-by: NGregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels.
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NDesmond Liu <desmondl@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: NJonathan Richardson <jonathar@broadcom.com>
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Some chips, such as BCM6328, only require bcm7120-l2.  Some BCM7xxx STB
configurations only require brcmstb-l2.  Treat them as two separate
entities, and update the mach-bcm dependencies to reflect the change.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

These are either implied or not necessary.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added
in commit 4fbe66d9 but was reverted in
commit fc3e825f to address some late
review comments. This reintroduces SMP support.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum required code
boot Linux on this SoC.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

There were several issues (of varying degree of importance) pointed out
with this code late in the review cycle, yet the code was still merged.
Let's rip it out for now and look at resubmitting at a later time.

This reverts most of commit 4fbe66d9.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMatt Porter <mporter@linaro.org>

The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.

This patch adds machine support for the ARM-based Broadcom SoCs.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NMatt Porter <mporter@linaro.org>

This patch adds SMP support for BCM281XX and BCM21664 family SoCs.

This feature is controlled with a distinct config option such that
an SMP-enabled multi-v7 binary can be configured to run these SoCs
in uniprocessor mode.  Since this SMP functionality is used for
multiple Broadcom mobile chip families the config option is called
ARCH_BCM_MOBILE_SMP (for lack of a better name).

On SoCs of this type, the secondary core is not held in reset on
power-on.  Instead it loops in a ROM-based holding pen.  To release
it, one must write into a special register a jump address whose
low-order bits have been replaced with a secondary core's id, then
trigger an event with SEV.  On receipt of an event, the ROM code
will examine the register's contents, and if the low-order bits
match its cpu id, it will clear them and write the value back to the
register just prior to jumping to the address specified.

The location of the special register is defined in the device tree
using a "secondary-boot-reg" property in a node whose "enable-method"
matches.

Derived from code originally provided by Ray Jui <rjui@broadcom.com>
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

A number of board files in arch/arm and arch/unicore32
explicitly reference platform_bus device as a parent
for new platform devices.

This is unnecessary, as platform device API guarantees
that devices with NULL parent are going to by adopted
by the mentioned "root" device.

This patch removes or replaces with NULL such references.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The System Type menu is getting quite long with platforms and is
inconsistent in handling of sub-arch specific options. Tidy up the menu
by making platform options a menuconfig entry containing any platform
specific config items.

[arnd: change OMAP part according to suggestion from
 Tony Lindgren <tony@atomide.com>]
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  We can remove the explicit machine init too
as this becomes identical to the generic version.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When targetting ARCH_MULTIPLATFORM, we may include support for SoCs with
PCI-capable devices (e.g. mach-virt with virtio-pci).

This patch allows PCI support to be selected for these SoCs by selecting
CONFIG_MIGHT_HAVE_PCI when CONFIG_ARCH_MULTIPLATFORM=y and removes the
individual selections from multi-platform enabled SoCs.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

They're u32, they're not unsigned long.  The UL suffix is not required
here.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

ARM_ERRATA_775420 needs to be enabled.

A data cache maintenance operation which aborts, followed by an ISB,
without any DSB in-between, might lead to deadlock.

Affects: bug present in Cortex-A9 r3p0 and earlier. Fixed in r4p0.

Cortex-A9 r3p0 is used in a multitude of Broadcom parts including
the bcm21664, bcm281xx, 5301x families of devices.
Signed-off-by: NScott Branden <sbranden@broadcom.com>
Tested-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Currently, Broadcom SoC options are shown whenever ARCH_MULTIPLATFORM
is enabled. Restrict this so they are only seen when ARCH_MULTI_V6_V7
variants are enabled.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
[mporter: added commit log message]
Signed-off-by: NMatt Porter <mporter@linaro.org>

These source files contain only level-2 cache initialization code,
so rename them to make that fact more obvious.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

The block of comments in bcm_kona_do_smc() are somewhat confusing.
This patch attempts to clarify what's going on.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Move the code that implements the "smc" call into a C function that
uses inline assembly.  This allows us to make that function private,
and enables us to get rid of "arch/arm/mach-bcm/bcm_kona_smc_asm.S".
Rename what had been the "buffer_addr" argument to be "buffer_phys"
so it's consistent with other usage in this file.

Since it's now easy to do, verify that r12 contains SEC_EXIT_NORMAL
upon completion of the SMC.  There really isn't a good way to handle
the abnormal completion of a secure monitor request.

Since "bcm_kona_smc.h" is now only included from C files, eliminate
the #ifndef __ASSEMBLY__.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Clean up a few header file includes, eliminating a few that are not
really needed and putting in their place some that are.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support
for level-2 cache to be enabled or disabled at build time for
BCM218XX and BCM21664 family SoCs.

Build support for SMC only if it's required (currently it's only
required for to support level 2 cache control).

If arch/arm/mach-bcm/kona.c gets compiled, ARCH_BCM_MOBILE_L2_CACHE
must have been selected, which implies CONFIG_CACHE_L2X0 is set.
There is therefore no need to check CONFIG_CACHE_L2X0 at the top
of kona_l2_cache_init(), so get rid of that check.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

There's logic in bcm_kona_smc() to ensure __bcm_kona_smc() gets
called on CPU 0; if already executing on CPU 0, that function is
called directly.  The direct call is not protected from interrupts,
however, which is not safe.

Note that smp_call_function_single() is designed to handle the case
where the target cpu is the current one.  It also gets a reference
to the CPU and disables IRQs across the call.

So we can simplify things and at the same time be protected against
interrupts by calling smp_call_function_single() unconditionally.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Currently it is assumed that SEC_ROM_RET_OK is the only valid "good"
result of a secure monitor request.  However the values that can be
returned by a secure monitor request are dependent on which service
id was provided.

We therefore should handle the result in a request-dependent way.
The most natural way to do that is to have the initiator of the
request--where bcm_kona_smc() is called--handle the result in a way
appropriate to the request.

An "smc" operation must be performed only on core 0, while the
request can be initiated from any core.  To pass back the request
result, we add a new field to the bcm_kona_smc_data structure, and
have bcm_kona_smc() return that value rather than 0.

There's only one caller right now.  Move the existing check of the
result out of __bcm_kona_smc() and into the kona_l2_cache_init()
where the SSAPI_ENABLE_L2_CACHE request is initiated.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

This patch just does some simple cleanup in "bcm_kona_smc.c":
    - Get rid of the secure_bridge_data structure.  Instead, just
      define two globals that record the physical and virtual
      addresses of the SMC arguments buffer.  Use "buffer" instead
      of "bounce" in their names.  Drop of the erroneous __iomem
      annotation for the physical address.
    - Get rid of the initialized flag and just use a non-null buffer
      address to indicate that.
    - Get the size of the memory region when fetching the SMC
      arguments buffer location from the device tree.  Use it to
      call ioremap() directly rather than requiring of_iomap() to
      go look it up again.
    - Do some additional validation on that memory region size.
    - Flush caches unconditionally in __bcm_kona_smc(); nothing
      supplies SSAPI_BRCM_START_VC_CORE as a service id.
    - Drop a needless initialization of "rc" in __bcm_kona_smc().

It also deletes most of the content of "bcm_kona_smc.h" because it's
never actually used and is of questionable value anyway.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>