All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Tested-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Enable smp for HiP01 board.
Signed-off-by: NWang Long <long.wanglong@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
[olof: split off the dts change to a separate commit]
Signed-off-by: NOlof Johansson <olof@lixom.net>

As hix5hd2 and hip01 has the same secondary_startup
so rename hix5hd2_secondary_startup to
to hisi_secondary_startup.

the hip01 will use hisi_secondary_startup for the
secondary core boot.
Signed-off-by: NWang Long <long.wanglong@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

As hix5hd2 and hip01 has the same .smp_prepare_cpus
in struct smp_operations, so rename hix5hd2_smp_prepare_cpus
to hisi_common_smp_prepare_cpus.

the hip01 will use hisi_common_smp_prepare_cpus in its
struct smp_operations.
Signed-off-by: NWang Long <long.wanglong@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Use CPU_METHOD_OF_DECLARE() instead. And declare smp method in dts file.

Changelog:
v6:
  * Use hisilicon,hi3620-smp as enable-method property in Hi3620 dts.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.

Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.

They are different in implementation such as SMP, IPs integarted and
earlycon configure.
Signed-off-by: NHaifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: NJiancheng Xue <jchxue@gmail.com>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NWei Xu <xuwei5@hisilicon.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Since some new Hisilicon SoCs are not named as hi3xxx, rename mach-hi3xxx
to mach-hisi instead. And the pronounciation of "hisi" is similar to the
chinese pronounciation of Hisilicon. So Hisilicon guys like this name.

ARCH_HI3xxx will be renamed later since other drivers are using it and
they are still in linux-next git tree. So rename ARCH_HI3xxx later.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Enable hotplug support on hi3xxx platform

How to test:
cat proc/interrupts
echo 0 > /sys/devices/system/cpu/cpuX/online
cat proc/interrupts
echo 1 > /sys/devices/system/cpu/cpuX/online
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: NZhang Mingjun <zhang.mingjun@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fixed checkpatch error]
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Enable SMP support on hi3xxx platform
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: NZhang Mingjun <zhang.mingjun@linaro.org>
Tested-by: NLi Xin <li.xin@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fix checkpatch errors]
Signed-off-by: NKevin Hilman <khilman@linaro.org>