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  1. 28 1月, 2010 1 次提交
    • D
      MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs · 010c108d
      由 David VomLehn 提交于 
      The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      010c108d
  3. 17 6月, 2009 1 次提交
  5. 14 5月, 2009 3 次提交
  7. 24 3月, 2009 1 次提交
  9. 11 1月, 2009 2 次提交
  11. 28 10月, 2008 1 次提交
  13. 11 10月, 2008 1 次提交
  15. 04 10月, 2008 1 次提交
  17. 06 6月, 2008 1 次提交
  19. 12 10月, 2007 1 次提交
  21. 13 7月, 2007 1 次提交
  23. 11 7月, 2007 2 次提交
  25. 06 7月, 2007 1 次提交
    • R
      [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores · 4b3e975e
      由 Ralf Baechle 提交于 
      The idle loop goes to sleep using the WAIT instruction if !need_resched().
This has is suffering from from a race condition that if if just after
need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
we've just completed the test so go to sleep anyway.  This would be
trivial to fix by just disabling interrupts during that sequence as in:

        local_irq_disable();
        if (!need_resched())
                __asm__("wait");
        local_irq_enable();

but the processor architecture leaves it undefined if a processor calling
WAIT with interrupts disabled will ever restart its pipeline and indeed
some processors have made use of the freedom provided by the architecture
definition.  This has been resolved and the Config7.WII bit indicates that
the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
74K starting revision 2.1.0 so enable the use of WAIT with interrupts
disabled for 74K based on a c0_prid of at least that.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4b3e975e
  27. 30 11月, 2006 1 次提交
  29. 14 7月, 2006 3 次提交
  31. 30 6月, 2006 1 次提交
  33. 20 6月, 2006 1 次提交
  35. 01 6月, 2006 1 次提交
  37. 26 4月, 2006 1 次提交
  39. 19 4月, 2006 2 次提交
  41. 10 1月, 2006 1 次提交
  43. 30 10月, 2005 12 次提交