arm64: kernel: disable CNP on LINXICORE9100

hulk inclusion
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/I7F28R
CVE: NA

--------------------------------

On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when
TTBRx.CNP=1 differs from the standard ARM core. This causes issues when tlb
entries sharing between CPU cores. Avoid these issues by disabling CNP
feature for Hisilicon LINXICORE9100 cores.
Signed-off-by: NTong Tiangen <tongtiangen@huawei.com>

Documentation/arm64/silicon-errata.rst

@@ -151,6 +151,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Hisilicon      | Hip09           | #162100801      | HISILICON_ERRATUM_162100801 |
 +----------------+-----------------+-----------------+-----------------------------+
+| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 +----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

@@ -812,6 +812,17 @@ config HISILICON_ERRATUM_162100801
 
 	If unsure, say Y.
 
+config HISILICON_ERRATUM_162100125
+	bool "Hisilicon erratum 162100125"
+	default y
+	help
+	  On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when
+	  TTBRx.CNP=1 differs from the standard ARM core. This causes issues when
+	  tlb entries sharing between CPU cores. Avoid these issues by disabling
+	  CNP support for Hisilicon LINXICORE9100 cores.
+
+	  If unsure, say Y.
+
 config QCOM_FALKOR_ERRATUM_1003
 	bool "Falkor E1003: Incorrect translation due to ASID change"
 	default y

arch/arm64/configs/openeuler_defconfig

@@ -391,6 +391,7 @@ CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
 CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y
 # CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set
 CONFIG_HISILICON_ERRATUM_162100801=y
+CONFIG_HISILICON_ERRATUM_162100125=y
 # end of ARM errata workarounds via the alternatives framework
 
 CONFIG_ARM64_4K_PAGES=y

arch/arm64/include/asm/cpucaps.h

@@ -74,6 +74,7 @@
 #define ARM64_SPECTRE_BHB			66
 #define ARM64_WORKAROUND_1742098	67
 #define ARM64_HAS_WFXT				68
+#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125	69
 
 #define ARM64_NCAPS				80
 

arch/arm64/include/asm/cputype.h

@@ -111,6 +111,7 @@
 
 #define HISI_CPU_PART_TSV110		0xD01
 #define HISI_CPU_PART_TSV200		0xD02
+#define HISI_CPU_PART_LINXICORE9100	0xD02
 
 #define PHYTIUM_CPU_PART_1500A		0X660
 #define PHYTIUM_CPU_PART_2000AHK	0X661
@@ -161,6 +162,7 @@
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 #define MIDR_HISI_TSV200 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV200)
+#define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100)
 #define MIDR_FT_1500A    MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_1500A)
 #define MIDR_FT_2000AHK	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000AHK)
 #define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)

arch/arm64/kernel/cpu_errata.c

@@ -324,6 +324,13 @@ static const struct midr_range cavium_erratum_30115_cpus[] = {
 };
 #endif
 
+#ifdef CONFIG_HISILICON_ERRATUM_162100125
+static const struct midr_range hisilicon_erratum_162100125_cpus[] = {
+	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),
+	{},
+};
+#endif
+
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
 	{
@@ -519,6 +526,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 		.cpu_enable = hisilicon_1980005_enable,
 	},
 #endif
+#ifdef CONFIG_HISILICON_ERRATUM_162100125
+	{
+		.desc = "Hisilicon erratum 162100125",
+		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100125,
+		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),
+	},
+#endif
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 	{
 		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",

arch/arm64/kernel/cpufeature.c

@@ -1330,6 +1330,9 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 	 if (is_kdump_kernel())
 		return false;
 
+	if (cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100125))
+		return false;
+
 	return has_cpuid_feature(entry, scope);
 }