diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 2305def38396b4f3afe6ecdf1d536989e4770e06..41728b336105854411e7fdc15d665a8024fa4680 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -151,6 +151,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Hisilicon      | Hip09           | #162100801      | HISILICON_ERRATUM_162100801 |
 +----------------+-----------------+-----------------+-----------------------------+
+| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e0143a3a99378a99bc744071d86dda43e3e9dde6..9a238d0882458a6b9dd528078ef5fbaf4e5d3f3e 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -812,6 +812,17 @@ config HISILICON_ERRATUM_162100801
 
 	If unsure, say Y.
 
+config HISILICON_ERRATUM_162100125
+	bool "Hisilicon erratum 162100125"
+	default y
+	help
+	  On Hisilicon LINXICORE9100 cores, sharing tlb entries on two cores when
+	  TTBRx.CNP=1 differs from the standard ARM core. This causes issues when
+	  tlb entries sharing between CPU cores. Avoid these issues by disabling
+	  CNP support for Hisilicon LINXICORE9100 cores.
+
+	  If unsure, say Y.
+
 config QCOM_FALKOR_ERRATUM_1003
 	bool "Falkor E1003: Incorrect translation due to ASID change"
 	default y
diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig
index 49e6d4734c59c44453a45c850a5805714d412956..eb4ee05224466f3cd5da6bce336ae5250a825159 100644
--- a/arch/arm64/configs/openeuler_defconfig
+++ b/arch/arm64/configs/openeuler_defconfig
@@ -391,6 +391,7 @@ CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
 CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y
 # CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set
 CONFIG_HISILICON_ERRATUM_162100801=y
+CONFIG_HISILICON_ERRATUM_162100125=y
 # end of ARM errata workarounds via the alternatives framework
 
 CONFIG_ARM64_4K_PAGES=y
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 37240e1f553c14a675ef611c22e89e5c45cb0ada..b43f8e3741148ca407da103951584f36e22d225c 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -74,6 +74,7 @@
 #define ARM64_SPECTRE_BHB			66
 #define ARM64_WORKAROUND_1742098	67
 #define ARM64_HAS_WFXT				68
+#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100125	69
 
 #define ARM64_NCAPS				80
 
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 812781fba3f94cedd1ac9288e333961bda16e5c4..e6b0ec40932d68ecf62c065b89562095a04f173c 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -111,6 +111,7 @@
 
 #define HISI_CPU_PART_TSV110		0xD01
 #define HISI_CPU_PART_TSV200		0xD02
+#define HISI_CPU_PART_LINXICORE9100	0xD02
 
 #define PHYTIUM_CPU_PART_1500A		0X660
 #define PHYTIUM_CPU_PART_2000AHK	0X661
@@ -161,6 +162,7 @@
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 #define MIDR_HISI_TSV200 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV200)
+#define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100)
 #define MIDR_FT_1500A    MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_1500A)
 #define MIDR_FT_2000AHK	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000AHK)
 #define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0955af96391b7924ed7b4a12e3befd847a59e4d5..7f175b3aac152f3b7d9b2e24dc347b4b72cd0a45 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -324,6 +324,13 @@ static const struct midr_range cavium_erratum_30115_cpus[] = {
 };
 #endif
 
+#ifdef CONFIG_HISILICON_ERRATUM_162100125
+static const struct midr_range hisilicon_erratum_162100125_cpus[] = {
+	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),
+	{},
+};
+#endif
+
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
 	{
@@ -519,6 +526,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 		.cpu_enable = hisilicon_1980005_enable,
 	},
 #endif
+#ifdef CONFIG_HISILICON_ERRATUM_162100125
+	{
+		.desc = "Hisilicon erratum 162100125",
+		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100125,
+		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),
+	},
+#endif
 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 	{
 		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3b746db0f40c57ee8808b5789a0234652ef0e499..57631fa553f68794da9419a703053b0dfa02f3f5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1330,6 +1330,9 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 	 if (is_kdump_kernel())
 		return false;
 
+	if (cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100125))
+		return false;
+
 	return has_cpuid_feature(entry, scope);
 }