perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support

mainline inclusion
from mainline-v5.15-rc1
commit f85ef898
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO

Intel-SIG: commit f85ef898 perf/x86/intel/uncore: Add Sapphire
Rapids server M2PCIe support
This commit is backported for SPR PMU uncore support.

-------------------------------------

M2PCIe* blocks manage the interface between the mesh and each IIO stack.

The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.
Signed-off-by: NKan Liang <kan.liang@linux.intel.com>
Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: NAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.comSigned-off-by: NYunying Sun <yunying.sun@intel.com>
Signed-off-by: NAichun Shi <aichun.shi@intel.com>

arch/x86/events/intel/uncore_snbep.c

@@ -5482,13 +5482,18 @@ static struct intel_uncore_type spr_uncore_irp = {
 
 };
 
+static struct intel_uncore_type spr_uncore_m2pcie = {
+	SPR_UNCORE_COMMON_FORMAT(),
+	.name			= "m2pcie",
+};
+
 #define UNCORE_SPR_NUM_UNCORE_TYPES		12
 
 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
 	&spr_uncore_chabox,
 	&spr_uncore_iio,
 	&spr_uncore_irp,
-	NULL,
+	&spr_uncore_m2pcie,
 	NULL,
 	NULL,
 	NULL,