From c82c825cf08b38dc076ce9cb5a6b6028fa15160f Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Wed, 30 Jun 2021 14:08:29 -0700 Subject: [PATCH] perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support mainline inclusion from mainline-v5.15-rc1 commit f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7 category: feature feature: SPR PMU uncore support bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO Intel-SIG: commit f85ef898f884 perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support This commit is backported for SPR PMU uncore support. ------------------------------------- M2PCIe* blocks manage the interface between the mesh and each IIO stack. The layout of the control registers for a M2PCIe uncore unit is similar to a IRP uncore unit. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andi Kleen Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com Signed-off-by: Yunying Sun Signed-off-by: Aichun Shi --- arch/x86/events/intel/uncore_snbep.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 318587abf374..486c5b6ed727 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5482,13 +5482,18 @@ static struct intel_uncore_type spr_uncore_irp = { }; +static struct intel_uncore_type spr_uncore_m2pcie = { + SPR_UNCORE_COMMON_FORMAT(), + .name = "m2pcie", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { &spr_uncore_chabox, &spr_uncore_iio, &spr_uncore_irp, - NULL, + &spr_uncore_m2pcie, NULL, NULL, NULL, -- GitLab