perf/x86/intel/uncore: Add Sapphire Rapids server IRP support
mainline inclusion from mainline-v5.15-rc1 commit e199eb51 category: feature feature: SPR PMU uncore support bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO Intel-SIG: commit e199eb51 perf/x86/intel/uncore: Add Sapphire Rapids server IRP support This commit is backported for SPR PMU uncore support. ------------------------------------- The IRP is responsible for maintaining coherency for the IIO traffic targeting coherent memory. The layout of the control registers for a IRP uncore unit is a little bit different from the generic one. Factor out SPR_UNCORE_COMMON_FORMAT, which can be reused by the following uncore units. Signed-off-by: NKan Liang <kan.liang@linux.intel.com> Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: NAndi Kleen <ak@linux.intel.com> Link: https://lore.kernel.org/r/1625087320-194204-5-git-send-email-kan.liang@linux.intel.comSigned-off-by: NYunying Sun <yunying.sun@intel.com> Signed-off-by: NAichun Shi <aichun.shi@intel.com>
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