sw64: pcie: fix piu configuration to ensure data correctness

Sunway inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I5PNFK

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If a device does not use msi but uses polling as the completion flag
of DMAW events, the current PIUCONFIG0 register configuration can not
guarantee completion order of DMAW. It may happen that completion flag
has been polled before data written to memory, causing users to access
incorrect data.

To ensure correctness of data, DMAW order on PIU should be controlled.
That is, DMAW request with Relaxed Ordering off has to wait until the
previous write request receive response before submitting it.

This will significantly degrade DMAW performance for devices without
Relaxed Ordering capability.
Signed-off-by: NZhou Xuemei <zhouxuemei@wxiat.com>
Signed-off-by: NGu Zitao <guzitao@wxiat.com>

arch/sw_64/chip/chip3/chip.c

@@ -393,7 +393,6 @@ static void chip3_set_rc_piu(unsigned long node, unsigned long index)
 	/* set DMA offset value PCITODMA_OFFSET */
 	write_piu_ior0(node, index, EPDMABAR, PCITODMA_OFFSET);
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		write_piu_ior0(node, index, PIUCONFIG0, 0x38076);
 		write_piu_ior0(node, index, MSIADDR, MSIX_MSG_ADDR);
 		for (i = 0; i < 256; i++)
 			write_piu_ior0(node, index, MSICONFIG0 + (i << 7), 0);