From bd3127224a37d5839dc588c0c12581da19a96882 Mon Sep 17 00:00:00 2001 From: Zhou Xuemei Date: Thu, 25 Aug 2022 14:15:08 +0800 Subject: [PATCH] sw64: pcie: fix piu configuration to ensure data correctness Sunway inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I5PNFK -------------------------------- If a device does not use msi but uses polling as the completion flag of DMAW events, the current PIUCONFIG0 register configuration can not guarantee completion order of DMAW. It may happen that completion flag has been polled before data written to memory, causing users to access incorrect data. To ensure correctness of data, DMAW order on PIU should be controlled. That is, DMAW request with Relaxed Ordering off has to wait until the previous write request receive response before submitting it. This will significantly degrade DMAW performance for devices without Relaxed Ordering capability. Signed-off-by: Zhou Xuemei Signed-off-by: Gu Zitao --- arch/sw_64/chip/chip3/chip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/sw_64/chip/chip3/chip.c b/arch/sw_64/chip/chip3/chip.c index 8697891e3930..105389d5989f 100644 --- a/arch/sw_64/chip/chip3/chip.c +++ b/arch/sw_64/chip/chip3/chip.c @@ -393,7 +393,6 @@ static void chip3_set_rc_piu(unsigned long node, unsigned long index) /* set DMA offset value PCITODMA_OFFSET */ write_piu_ior0(node, index, EPDMABAR, PCITODMA_OFFSET); if (IS_ENABLED(CONFIG_PCI_MSI)) { - write_piu_ior0(node, index, PIUCONFIG0, 0x38076); write_piu_ior0(node, index, MSIADDR, MSIX_MSG_ADDR); for (i = 0; i < 256; i++) write_piu_ior0(node, index, MSICONFIG0 + (i << 7), 0); -- GitLab