perf/x86/intel/uncore: Fix Intel SPR CHA event constraints

mainline inclusion
from mainline-v5.16-rc1
commit 9d756e40
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO

Intel-SIG: commit 9d756e40 perf/x86/intel/uncore: Fix Intel SPR CHA
event constraints
This commit is backported as a fix to SPR PMU uncore support.

-------------------------------------

SPR CHA events have the exact same event constraints as SKX, so add the
constraints.

Fixes: 949b1138 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: NStephane Eranian <eranian@google.com>
Signed-off-by: NKan Liang <kan.liang@linux.intel.com>
Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-5-git-send-email-kan.liang@linux.intel.comSigned-off-by: NYunying Sun <yunying.sun@intel.com>

arch/x86/events/intel/uncore_snbep.c

@@ -5482,6 +5482,7 @@ static struct intel_uncore_type spr_uncore_chabox = {
 	.event_mask		= SPR_CHA_PMON_EVENT_MASK,
 	.event_mask_ext		= SPR_RAW_EVENT_MASK_EXT,
 	.num_shared_regs	= 1,
+	.constraints		= skx_uncore_chabox_constraints,
 	.ops			= &spr_uncore_chabox_ops,
 	.format_group		= &spr_uncore_chabox_format_group,
 	.attr_update		= uncore_alias_groups,