From 3ec8caa2278a2d9908b2d53596be31b572d5b49c Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Thu, 26 Aug 2021 08:32:40 -0700 Subject: [PATCH] perf/x86/intel/uncore: Fix Intel SPR CHA event constraints mainline inclusion from mainline-v5.16-rc1 commit 9d756e408e080d40e7916484b00c802026e6d1ad category: feature feature: SPR PMU uncore support bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO Intel-SIG: commit 9d756e408e08 perf/x86/intel/uncore: Fix Intel SPR CHA event constraints This commit is backported as a fix to SPR PMU uncore support. ------------------------------------- SPR CHA events have the exact same event constraints as SKX, so add the constraints. Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support") Reported-by: Stephane Eranian Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/1629991963-102621-5-git-send-email-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/intel/uncore_snbep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index bc672bd62e5d..4fadbf45e61a 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5482,6 +5482,7 @@ static struct intel_uncore_type spr_uncore_chabox = { .event_mask = SPR_CHA_PMON_EVENT_MASK, .event_mask_ext = SPR_RAW_EVENT_MASK_EXT, .num_shared_regs = 1, + .constraints = skx_uncore_chabox_constraints, .ops = &spr_uncore_chabox_ops, .format_group = &spr_uncore_chabox_format_group, .attr_update = uncore_alias_groups, -- GitLab