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    iommu/vt-d: Audit IOMMU Capabilities and add helper functions · ad3d1902
    Kyung Min Park 提交于
    Audit IOMMU Capability/Extended Capability and check if the IOMMUs have
    the consistent value for features. Report out or scale to the lowest
    supported when IOMMU features have incompatibility among IOMMUs.
    
    Report out features when below features are mismatched:
      - First Level 5 Level Paging Support (FL5LP)
      - First Level 1 GByte Page Support (FL1GP)
      - Read Draining (DRD)
      - Write Draining (DWD)
      - Page Selective Invalidation (PSI)
      - Zero Length Read (ZLR)
      - Caching Mode (CM)
      - Protected High/Low-Memory Region (PHMR/PLMR)
      - Required Write-Buffer Flushing (RWBF)
      - Advanced Fault Logging (AFL)
      - RID-PASID Support (RPS)
      - Scalable Mode Page Walk Coherency (SMPWC)
      - First Level Translation Support (FLTS)
      - Second Level Translation Support (SLTS)
      - No Write Flag Support (NWFS)
      - Second Level Accessed/Dirty Support (SLADS)
      - Virtual Command Support (VCS)
      - Scalable Mode Translation Support (SMTS)
      - Device TLB Invalidation Throttle (DIT)
      - Page Drain Support (PDS)
      - Process Address Space ID Support (PASID)
      - Extended Accessed Flag Support (EAFS)
      - Supervisor Request Support (SRS)
      - Execute Request Support (ERS)
      - Page Request Support (PRS)
      - Nested Translation Support (NEST)
      - Snoop Control (SC)
      - Pass Through (PT)
      - Device TLB Support (DT)
      - Queued Invalidation (QI)
      - Page walk Coherency (C)
    
    Set capability to the lowest supported when below features are mismatched:
      - Maximum Address Mask Value (MAMV)
      - Number of Fault Recording Registers (NFR)
      - Second Level Large Page Support (SLLPS)
      - Fault Recording Offset (FRO)
      - Maximum Guest Address Width (MGAW)
      - Supported Adjusted Guest Address Width (SAGAW)
      - Number of Domains supported (NDOMS)
      - Pasid Size Supported (PSS)
      - Maximum Handle Mask Value (MHMV)
      - IOTLB Register Offset (IRO)
    Signed-off-by: NKyung Min Park <kyung.min.park@intel.com>
    Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
    Link: https://lore.kernel.org/r/20210130184452.31711-1-kyung.min.park@intel.com
    Link: https://lore.kernel.org/r/20210204014401.2846425-3-baolu.lu@linux.intel.comSigned-off-by: NJoerg Roedel <jroedel@suse.de>
    ad3d1902
iommu.c 143.1 KB