exynos_mixer.c 33.2 KB
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/*
 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 * Authors:
 * Seung-Woo Kim <sw0312.kim@samsung.com>
 *	Inki Dae <inki.dae@samsung.com>
 *	Joonyoung Shim <jy0922.shim@samsung.com>
 *
 * Based on drivers/media/video/s5p-tv/mixer_reg.c
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

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#include <drm/drmP.h>
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#include "regs-mixer.h"
#include "regs-vp.h"

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/component.h>
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#include <drm/exynos_drm.h>

#include "exynos_drm_drv.h"
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_fb.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#define MIXER_WIN_NR		3
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#define VP_DEFAULT_WIN		2
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/*
 * Mixer color space conversion coefficient triplet.
 * Used for CSC from RGB to YCbCr.
 * Each coefficient is a 10-bit fixed point number with
 * sign and no integer part, i.e.
 * [0:8] = fractional part (representing a value y = x / 2^9)
 * [9] = sign
 * Negative values are encoded with two's complement.
 */
#define MXR_CSC_C(x) ((int)((x) * 512.0) & 0x3ff)
#define MXR_CSC_CT(a0, a1, a2) \
  ((MXR_CSC_C(a0) << 20) | (MXR_CSC_C(a1) << 10) | (MXR_CSC_C(a2) << 0))

/* YCbCr value, used for mixer background color configuration. */
#define MXR_YCBCR_VAL(y, cb, cr) (((y) << 16) | ((cb) << 8) | ((cr) << 0))

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/* The pixelformats that are natively supported by the mixer. */
#define MXR_FORMAT_RGB565	4
#define MXR_FORMAT_ARGB1555	5
#define MXR_FORMAT_ARGB4444	6
#define MXR_FORMAT_ARGB8888	7

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struct mixer_resources {
	int			irq;
	void __iomem		*mixer_regs;
	void __iomem		*vp_regs;
	spinlock_t		reg_slock;
	struct clk		*mixer;
	struct clk		*vp;
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	struct clk		*hdmi;
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	struct clk		*sclk_mixer;
	struct clk		*sclk_hdmi;
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	struct clk		*mout_mixer;
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};

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enum mixer_version_id {
	MXR_VER_0_0_0_16,
	MXR_VER_16_0_33_0,
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	MXR_VER_128_0_0_184,
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};

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enum mixer_flag_bits {
	MXR_BIT_POWERED,
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	MXR_BIT_VSYNC,
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	MXR_BIT_INTERLACE,
	MXR_BIT_VP_ENABLED,
	MXR_BIT_HAS_SCLK,
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};

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static const uint32_t mixer_formats[] = {
	DRM_FORMAT_XRGB4444,
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	DRM_FORMAT_ARGB4444,
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	DRM_FORMAT_XRGB1555,
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	DRM_FORMAT_ARGB1555,
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	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
};

static const uint32_t vp_formats[] = {
	DRM_FORMAT_NV12,
	DRM_FORMAT_NV21,
};

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struct mixer_context {
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	struct platform_device *pdev;
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	struct device		*dev;
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	struct drm_device	*drm_dev;
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	struct exynos_drm_crtc	*crtc;
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	struct exynos_drm_plane	planes[MIXER_WIN_NR];
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	unsigned long		flags;
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	struct mixer_resources	mixer_res;
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	enum mixer_version_id	mxr_ver;
};

struct mixer_drv_data {
	enum mixer_version_id	version;
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	bool					is_vp_enabled;
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	bool					has_sclk;
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};

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static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
	{
		.zpos = 0,
		.type = DRM_PLANE_TYPE_PRIMARY,
		.pixel_formats = mixer_formats,
		.num_pixel_formats = ARRAY_SIZE(mixer_formats),
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		.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
				EXYNOS_DRM_PLANE_CAP_ZPOS,
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	}, {
		.zpos = 1,
		.type = DRM_PLANE_TYPE_CURSOR,
		.pixel_formats = mixer_formats,
		.num_pixel_formats = ARRAY_SIZE(mixer_formats),
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		.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
				EXYNOS_DRM_PLANE_CAP_ZPOS,
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	}, {
		.zpos = 2,
		.type = DRM_PLANE_TYPE_OVERLAY,
		.pixel_formats = vp_formats,
		.num_pixel_formats = ARRAY_SIZE(vp_formats),
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		.capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
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				EXYNOS_DRM_PLANE_CAP_ZPOS |
				EXYNOS_DRM_PLANE_CAP_TILE,
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	},
};

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static const u8 filter_y_horiz_tap8[] = {
	0,	-1,	-1,	-1,	-1,	-1,	-1,	-1,
	-1,	-1,	-1,	-1,	-1,	0,	0,	0,
	0,	2,	4,	5,	6,	6,	6,	6,
	6,	5,	5,	4,	3,	2,	1,	1,
	0,	-6,	-12,	-16,	-18,	-20,	-21,	-20,
	-20,	-18,	-16,	-13,	-10,	-8,	-5,	-2,
	127,	126,	125,	121,	114,	107,	99,	89,
	79,	68,	57,	46,	35,	25,	16,	8,
};

static const u8 filter_y_vert_tap4[] = {
	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
	127,	126,	124,	118,	111,	102,	92,	81,
	70,	59,	48,	37,	27,	19,	11,	5,
	0,	5,	11,	19,	27,	37,	48,	59,
	70,	81,	92,	102,	111,	118,	124,	126,
	0,	0,	-1,	-1,	-2,	-3,	-4,	-5,
	-6,	-7,	-8,	-8,	-8,	-8,	-6,	-3,
};

static const u8 filter_cr_horiz_tap4[] = {
	0,	-3,	-6,	-8,	-8,	-8,	-8,	-7,
	-6,	-5,	-4,	-3,	-2,	-1,	-1,	0,
	127,	126,	124,	118,	111,	102,	92,	81,
	70,	59,	48,	37,	27,	19,	11,	5,
};

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static inline bool is_alpha_format(unsigned int pixel_format)
{
	switch (pixel_format) {
	case DRM_FORMAT_ARGB8888:
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	case DRM_FORMAT_ARGB1555:
	case DRM_FORMAT_ARGB4444:
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		return true;
	default:
		return false;
	}
}

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static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
{
	return readl(res->vp_regs + reg_id);
}

static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
				 u32 val)
{
	writel(val, res->vp_regs + reg_id);
}

static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
				 u32 val, u32 mask)
{
	u32 old = vp_reg_read(res, reg_id);

	val = (val & mask) | (old & ~mask);
	writel(val, res->vp_regs + reg_id);
}

static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
{
	return readl(res->mixer_regs + reg_id);
}

static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
				 u32 val)
{
	writel(val, res->mixer_regs + reg_id);
}

static inline void mixer_reg_writemask(struct mixer_resources *res,
				 u32 reg_id, u32 val, u32 mask)
{
	u32 old = mixer_reg_read(res, reg_id);

	val = (val & mask) | (old & ~mask);
	writel(val, res->mixer_regs + reg_id);
}

static void mixer_regs_dump(struct mixer_context *ctx)
{
#define DUMPREG(reg_id) \
do { \
	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
		(u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
} while (0)

	DUMPREG(MXR_STATUS);
	DUMPREG(MXR_CFG);
	DUMPREG(MXR_INT_EN);
	DUMPREG(MXR_INT_STATUS);

	DUMPREG(MXR_LAYER_CFG);
	DUMPREG(MXR_VIDEO_CFG);

	DUMPREG(MXR_GRAPHIC0_CFG);
	DUMPREG(MXR_GRAPHIC0_BASE);
	DUMPREG(MXR_GRAPHIC0_SPAN);
	DUMPREG(MXR_GRAPHIC0_WH);
	DUMPREG(MXR_GRAPHIC0_SXY);
	DUMPREG(MXR_GRAPHIC0_DXY);

	DUMPREG(MXR_GRAPHIC1_CFG);
	DUMPREG(MXR_GRAPHIC1_BASE);
	DUMPREG(MXR_GRAPHIC1_SPAN);
	DUMPREG(MXR_GRAPHIC1_WH);
	DUMPREG(MXR_GRAPHIC1_SXY);
	DUMPREG(MXR_GRAPHIC1_DXY);
#undef DUMPREG
}

static void vp_regs_dump(struct mixer_context *ctx)
{
#define DUMPREG(reg_id) \
do { \
	DRM_DEBUG_KMS(#reg_id " = %08x\n", \
		(u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
} while (0)

	DUMPREG(VP_ENABLE);
	DUMPREG(VP_SRESET);
	DUMPREG(VP_SHADOW_UPDATE);
	DUMPREG(VP_FIELD_ID);
	DUMPREG(VP_MODE);
	DUMPREG(VP_IMG_SIZE_Y);
	DUMPREG(VP_IMG_SIZE_C);
	DUMPREG(VP_PER_RATE_CTRL);
	DUMPREG(VP_TOP_Y_PTR);
	DUMPREG(VP_BOT_Y_PTR);
	DUMPREG(VP_TOP_C_PTR);
	DUMPREG(VP_BOT_C_PTR);
	DUMPREG(VP_ENDIAN_MODE);
	DUMPREG(VP_SRC_H_POSITION);
	DUMPREG(VP_SRC_V_POSITION);
	DUMPREG(VP_SRC_WIDTH);
	DUMPREG(VP_SRC_HEIGHT);
	DUMPREG(VP_DST_H_POSITION);
	DUMPREG(VP_DST_V_POSITION);
	DUMPREG(VP_DST_WIDTH);
	DUMPREG(VP_DST_HEIGHT);
	DUMPREG(VP_H_RATIO);
	DUMPREG(VP_V_RATIO);

#undef DUMPREG
}

static inline void vp_filter_set(struct mixer_resources *res,
		int reg_id, const u8 *data, unsigned int size)
{
	/* assure 4-byte align */
	BUG_ON(size & 3);
	for (; size; size -= 4, reg_id += 4, data += 4) {
		u32 val = (data[0] << 24) |  (data[1] << 16) |
			(data[2] << 8) | data[3];
		vp_reg_write(res, reg_id, val);
	}
}

static void vp_default_filter(struct mixer_resources *res)
{
	vp_filter_set(res, VP_POLY8_Y0_LL,
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		filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
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	vp_filter_set(res, VP_POLY4_Y0_LL,
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		filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
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	vp_filter_set(res, VP_POLY4_C0_LL,
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		filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
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}

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static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
				bool alpha)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

	val  = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
	if (alpha) {
		/* blending based on pixel alpha */
		val |= MXR_GRP_CFG_BLEND_PRE_MUL;
		val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
	}
	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
			    val, MXR_GRP_CFG_MISC_MASK);
}

static void mixer_cfg_vp_blend(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

	/*
	 * No blending at the moment since the NV12/NV21 pixelformats don't
	 * have an alpha channel. However the mixer supports a global alpha
	 * value for a layer. Once this functionality is exposed, we can
	 * support blending of the video layer through this.
	 */
	val = 0;
	mixer_reg_write(res, MXR_VIDEO_CFG, val);
}

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static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
{
	struct mixer_resources *res = &ctx->mixer_res;

	/* block update on vsync */
	mixer_reg_writemask(res, MXR_STATUS, enable ?
			MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);

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	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
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		vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
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			VP_SHADOW_UPDATE_ENABLE : 0);
}

static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

	/* choosing between interlace and progressive mode */
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	val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ?
		MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE;
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	if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
		/* choosing between proper HD and SD mode */
		if (height <= 480)
			val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
		else if (height <= 576)
			val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
		else if (height <= 720)
			val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
		else if (height <= 1080)
			val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
		else
			val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
	}
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	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
}

static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val;

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	switch (height) {
	case 480:
	case 576:
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		val = MXR_CFG_RGB601_0_255;
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		break;
	case 720:
	case 1080:
	default:
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		val = MXR_CFG_RGB709_16_235;
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		/* Configure the BT.709 CSC matrix for full range RGB. */
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		mixer_reg_write(res, MXR_CM_COEFF_Y,
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			MXR_CSC_CT( 0.184,  0.614,  0.063) |
			MXR_CM_COEFF_RGB_FULL);
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		mixer_reg_write(res, MXR_CM_COEFF_CB,
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			MXR_CSC_CT(-0.102, -0.338,  0.440));
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		mixer_reg_write(res, MXR_CM_COEFF_CR,
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			MXR_CSC_CT( 0.440, -0.399, -0.040));
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		break;
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	}

	mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}

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static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
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			    unsigned int priority, bool enable)
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{
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val = enable ? ~0 : 0;

	switch (win) {
	case 0:
		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
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		mixer_reg_writemask(res, MXR_LAYER_CFG,
				    MXR_LAYER_CFG_GRP0_VAL(priority),
				    MXR_LAYER_CFG_GRP0_MASK);
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		break;
	case 1:
		mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
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		mixer_reg_writemask(res, MXR_LAYER_CFG,
				    MXR_LAYER_CFG_GRP1_VAL(priority),
				    MXR_LAYER_CFG_GRP1_MASK);
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		break;
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	case VP_DEFAULT_WIN:
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		if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
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			vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
			mixer_reg_writemask(res, MXR_CFG, val,
				MXR_CFG_VP_ENABLE);
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			mixer_reg_writemask(res, MXR_LAYER_CFG,
					    MXR_LAYER_CFG_VP_VAL(priority),
					    MXR_LAYER_CFG_VP_MASK);
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		}
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		break;
	}
}

static void mixer_run(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;

	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
}

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static void mixer_stop(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	int timeout = 20;

	mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);

	while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
			--timeout)
		usleep_range(10000, 12000);
}

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static void vp_video_buffer(struct mixer_context *ctx,
			    struct exynos_drm_plane *plane)
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{
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	struct exynos_drm_plane_state *state =
				to_exynos_plane_state(plane->base.state);
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	struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
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	struct mixer_resources *res = &ctx->mixer_res;
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	struct drm_framebuffer *fb = state->base.fb;
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	unsigned int priority = state->base.normalized_zpos + 1;
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	unsigned long flags;
	dma_addr_t luma_addr[2], chroma_addr[2];
	bool tiled_mode = false;
	bool crcb_mode = false;
	u32 val;

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	switch (fb->format->format) {
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	case DRM_FORMAT_NV12:
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		crcb_mode = false;
		break;
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	case DRM_FORMAT_NV21:
		crcb_mode = true;
		break;
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	default:
		DRM_ERROR("pixel format for vp is wrong [%d].\n",
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				fb->format->format);
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		return;
	}

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	if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
		tiled_mode = true;

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	luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
	chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
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	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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		__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
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		if (tiled_mode) {
			luma_addr[1] = luma_addr[0] + 0x40;
			chroma_addr[1] = chroma_addr[0] + 0x40;
		} else {
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			luma_addr[1] = luma_addr[0] + fb->pitches[0];
			chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
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		}
	} else {
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		__clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
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		luma_addr[1] = 0;
		chroma_addr[1] = 0;
	}

	spin_lock_irqsave(&res->reg_slock, flags);

	/* interlace or progressive scan mode */
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	val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
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	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);

	/* setup format */
	val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
	val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);

	/* setting size of input image */
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	vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
		VP_IMG_VSIZE(fb->height));
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	/* chroma plane for NV12/NV21 is half the height of the luma plane */
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	vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
		VP_IMG_VSIZE(fb->height / 2));
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	vp_reg_write(res, VP_SRC_WIDTH, state->src.w);
	vp_reg_write(res, VP_SRC_HEIGHT, state->src.h);
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	vp_reg_write(res, VP_SRC_H_POSITION,
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			VP_SRC_H_POSITION_VAL(state->src.x));
	vp_reg_write(res, VP_SRC_V_POSITION, state->src.y);
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	vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
	vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
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	if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
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		vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2);
		vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2);
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	} else {
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		vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h);
		vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y);
557 558
	}

559 560
	vp_reg_write(res, VP_H_RATIO, state->h_ratio);
	vp_reg_write(res, VP_V_RATIO, state->v_ratio);
561 562 563 564 565 566 567 568 569

	vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);

	/* set buffer address to vp */
	vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
	vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
	vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
	vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);

570 571
	mixer_cfg_scan(ctx, mode->vdisplay);
	mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
572
	mixer_cfg_layer(ctx, plane->index, priority, true);
573
	mixer_cfg_vp_blend(ctx);
574 575 576 577
	mixer_run(ctx);

	spin_unlock_irqrestore(&res->reg_slock, flags);

578
	mixer_regs_dump(ctx);
579 580 581
	vp_regs_dump(ctx);
}

582 583 584 585
static void mixer_layer_update(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;

586
	mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
587 588
}

589 590
static void mixer_graph_buffer(struct mixer_context *ctx,
			       struct exynos_drm_plane *plane)
591
{
592 593
	struct exynos_drm_plane_state *state =
				to_exynos_plane_state(plane->base.state);
594
	struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
595
	struct mixer_resources *res = &ctx->mixer_res;
596
	struct drm_framebuffer *fb = state->base.fb;
597
	unsigned int priority = state->base.normalized_zpos + 1;
598
	unsigned long flags;
599
	unsigned int win = plane->index;
600
	unsigned int x_ratio = 0, y_ratio = 0;
601 602 603 604 605
	unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
	dma_addr_t dma_addr;
	unsigned int fmt;
	u32 val;

V
Ville Syrjälä 已提交
606
	switch (fb->format->format) {
607
	case DRM_FORMAT_XRGB4444:
608
	case DRM_FORMAT_ARGB4444:
609 610 611 612
		fmt = MXR_FORMAT_ARGB4444;
		break;

	case DRM_FORMAT_XRGB1555:
613
	case DRM_FORMAT_ARGB1555:
614 615
		fmt = MXR_FORMAT_ARGB1555;
		break;
616

617 618
	case DRM_FORMAT_RGB565:
		fmt = MXR_FORMAT_RGB565;
619
		break;
620 621 622 623

	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		fmt = MXR_FORMAT_ARGB8888;
624
		break;
625

626
	default:
627 628
		DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
		return;
629 630
	}

631 632 633
	/* ratio is already checked by common plane code */
	x_ratio = state->h_ratio == (1 << 15);
	y_ratio = state->v_ratio == (1 << 15);
634

635 636
	dst_x_offset = state->crtc.x;
	dst_y_offset = state->crtc.y;
637 638

	/* converting dma address base and source offset */
639
	dma_addr = exynos_drm_fb_dma_addr(fb, 0)
V
Ville Syrjälä 已提交
640
		+ (state->src.x * fb->format->cpp[0])
641
		+ (state->src.y * fb->pitches[0]);
642 643 644
	src_x_offset = 0;
	src_y_offset = 0;

645
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
646
		__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
647
	else
648
		__clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
649 650 651 652 653 654 655 656

	spin_lock_irqsave(&res->reg_slock, flags);

	/* setup format */
	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
		MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);

	/* setup geometry */
657
	mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
V
Ville Syrjälä 已提交
658
			fb->pitches[0] / fb->format->cpp[0]);
659

660 661
	/* setup display size */
	if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
662
		win == DEFAULT_WIN) {
663 664
		val  = MXR_MXR_RES_HEIGHT(mode->vdisplay);
		val |= MXR_MXR_RES_WIDTH(mode->hdisplay);
665 666 667
		mixer_reg_write(res, MXR_RESOLUTION, val);
	}

668 669
	val  = MXR_GRP_WH_WIDTH(state->src.w);
	val |= MXR_GRP_WH_HEIGHT(state->src.h);
670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686
	val |= MXR_GRP_WH_H_SCALE(x_ratio);
	val |= MXR_GRP_WH_V_SCALE(y_ratio);
	mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);

	/* setup offsets in source image */
	val  = MXR_GRP_SXY_SX(src_x_offset);
	val |= MXR_GRP_SXY_SY(src_y_offset);
	mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);

	/* setup offsets in display image */
	val  = MXR_GRP_DXY_DX(dst_x_offset);
	val |= MXR_GRP_DXY_DY(dst_y_offset);
	mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);

	/* set buffer address to mixer */
	mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);

687 688
	mixer_cfg_scan(ctx, mode->vdisplay);
	mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
689
	mixer_cfg_layer(ctx, win, priority, true);
V
Ville Syrjälä 已提交
690
	mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->format->format));
691 692

	/* layer update mandatory for mixer 16.0.33.0 */
693 694
	if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
		ctx->mxr_ver == MXR_VER_128_0_0_184)
695 696
		mixer_layer_update(ctx);

697 698 699
	mixer_run(ctx);

	spin_unlock_irqrestore(&res->reg_slock, flags);
700 701

	mixer_regs_dump(ctx);
702 703 704 705 706
}

static void vp_win_reset(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
707
	unsigned int tries = 100;
708 709

	vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
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Dan Carpenter 已提交
710
	while (--tries) {
711 712 713
		/* waiting until VP_SRESET_PROCESSING is 0 */
		if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
			break;
714
		mdelay(10);
715 716 717 718
	}
	WARN(tries == 0, "failed to reset Video Processor\n");
}

J
Joonyoung Shim 已提交
719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734
static void mixer_win_reset(struct mixer_context *ctx)
{
	struct mixer_resources *res = &ctx->mixer_res;
	unsigned long flags;

	spin_lock_irqsave(&res->reg_slock, flags);

	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);

	/* set output in RGB888 mode */
	mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);

	/* 16 beat burst in DMA */
	mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
		MXR_STATUS_BURST_MASK);

735 736
	/* reset default layer priority */
	mixer_reg_write(res, MXR_LAYER_CFG, 0);
J
Joonyoung Shim 已提交
737

738 739 740 741
	/* set all background colors to RGB (0,0,0) */
	mixer_reg_write(res, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128));
	mixer_reg_write(res, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128));
	mixer_reg_write(res, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128));
J
Joonyoung Shim 已提交
742

743
	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
744 745 746 747
		/* configuration of Video Processor Registers */
		vp_win_reset(ctx);
		vp_default_filter(res);
	}
J
Joonyoung Shim 已提交
748 749 750 751

	/* disable all layers */
	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
	mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
752
	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
753
		mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
J
Joonyoung Shim 已提交
754 755 756 757

	spin_unlock_irqrestore(&res->reg_slock, flags);
}

758 759 760 761 762 763 764 765 766 767 768 769 770
static irqreturn_t mixer_irq_handler(int irq, void *arg)
{
	struct mixer_context *ctx = arg;
	struct mixer_resources *res = &ctx->mixer_res;
	u32 val, base, shadow;

	spin_lock(&res->reg_slock);

	/* read interrupt status for handling and clearing flags for VSYNC */
	val = mixer_reg_read(res, MXR_INT_STATUS);

	/* handling VSYNC */
	if (val & MXR_INT_STATUS_VSYNC) {
771 772 773 774
		/* vsync interrupt use different bit for read and clear */
		val |= MXR_INT_CLEAR_VSYNC;
		val &= ~MXR_INT_STATUS_VSYNC;

775
		/* interlace scan need to check shadow register */
776
		if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
777 778 779 780 781 782 783 784 785 786 787
			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
			if (base != shadow)
				goto out;

			base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
			shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
			if (base != shadow)
				goto out;
		}

788
		drm_crtc_handle_vblank(&ctx->crtc->base);
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814
	}

out:
	/* clear interrupts */
	mixer_reg_write(res, MXR_INT_STATUS, val);

	spin_unlock(&res->reg_slock);

	return IRQ_HANDLED;
}

static int mixer_resources_init(struct mixer_context *mixer_ctx)
{
	struct device *dev = &mixer_ctx->pdev->dev;
	struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
	struct resource *res;
	int ret;

	spin_lock_init(&mixer_res->reg_slock);

	mixer_res->mixer = devm_clk_get(dev, "mixer");
	if (IS_ERR(mixer_res->mixer)) {
		dev_err(dev, "failed to get clock 'mixer'\n");
		return -ENODEV;
	}

815 816 817 818 819 820
	mixer_res->hdmi = devm_clk_get(dev, "hdmi");
	if (IS_ERR(mixer_res->hdmi)) {
		dev_err(dev, "failed to get clock 'hdmi'\n");
		return PTR_ERR(mixer_res->hdmi);
	}

821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867
	mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
	if (IS_ERR(mixer_res->sclk_hdmi)) {
		dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
		return -ENODEV;
	}
	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(dev, "get memory resource failed.\n");
		return -ENXIO;
	}

	mixer_res->mixer_regs = devm_ioremap(dev, res->start,
							resource_size(res));
	if (mixer_res->mixer_regs == NULL) {
		dev_err(dev, "register mapping failed.\n");
		return -ENXIO;
	}

	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
	if (res == NULL) {
		dev_err(dev, "get interrupt resource failed.\n");
		return -ENXIO;
	}

	ret = devm_request_irq(dev, res->start, mixer_irq_handler,
						0, "drm_mixer", mixer_ctx);
	if (ret) {
		dev_err(dev, "request interrupt failed.\n");
		return ret;
	}
	mixer_res->irq = res->start;

	return 0;
}

static int vp_resources_init(struct mixer_context *mixer_ctx)
{
	struct device *dev = &mixer_ctx->pdev->dev;
	struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
	struct resource *res;

	mixer_res->vp = devm_clk_get(dev, "vp");
	if (IS_ERR(mixer_res->vp)) {
		dev_err(dev, "failed to get clock 'vp'\n");
		return -ENODEV;
	}

868
	if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) {
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
		mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
		if (IS_ERR(mixer_res->sclk_mixer)) {
			dev_err(dev, "failed to get clock 'sclk_mixer'\n");
			return -ENODEV;
		}
		mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
		if (IS_ERR(mixer_res->mout_mixer)) {
			dev_err(dev, "failed to get clock 'mout_mixer'\n");
			return -ENODEV;
		}

		if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
			clk_set_parent(mixer_res->mout_mixer,
				       mixer_res->sclk_hdmi);
	}
884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900

	res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
	if (res == NULL) {
		dev_err(dev, "get memory resource failed.\n");
		return -ENXIO;
	}

	mixer_res->vp_regs = devm_ioremap(dev, res->start,
							resource_size(res));
	if (mixer_res->vp_regs == NULL) {
		dev_err(dev, "register mapping failed.\n");
		return -ENXIO;
	}

	return 0;
}

901
static int mixer_initialize(struct mixer_context *mixer_ctx,
902
			struct drm_device *drm_dev)
903 904
{
	int ret;
905 906
	struct exynos_drm_private *priv;
	priv = drm_dev->dev_private;
907

908
	mixer_ctx->drm_dev = drm_dev;
909 910 911 912 913 914 915 916

	/* acquire resources: regs, irqs, clocks */
	ret = mixer_resources_init(mixer_ctx);
	if (ret) {
		DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
		return ret;
	}

917
	if (test_bit(MXR_BIT_VP_ENABLED, &mixer_ctx->flags)) {
918 919 920 921 922 923 924 925
		/* acquire vp resources: regs, irqs, clocks */
		ret = vp_resources_init(mixer_ctx);
		if (ret) {
			DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
			return ret;
		}
	}

926
	return drm_iommu_attach_device(drm_dev, mixer_ctx->dev);
927 928
}

929
static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
930
{
931
	drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
932 933
}

934
static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
935
{
936
	struct mixer_context *mixer_ctx = crtc->ctx;
937 938
	struct mixer_resources *res = &mixer_ctx->mixer_res;

939 940
	__set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
941
		return 0;
942 943

	/* enable vsync interrupt */
944 945
	mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
	mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
946 947 948 949

	return 0;
}

950
static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
951
{
952
	struct mixer_context *mixer_ctx = crtc->ctx;
953 954
	struct mixer_resources *res = &mixer_ctx->mixer_res;

955 956 957
	__clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);

	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
958 959
		return;

960
	/* disable vsync interrupt */
961
	mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
962 963 964
	mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
}

965 966 967 968 969 970 971 972 973 974
static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
{
	struct mixer_context *mixer_ctx = crtc->ctx;

	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
		return;

	mixer_vsync_set_update(mixer_ctx, false);
}

975 976
static void mixer_update_plane(struct exynos_drm_crtc *crtc,
			       struct exynos_drm_plane *plane)
977
{
978
	struct mixer_context *mixer_ctx = crtc->ctx;
979

980
	DRM_DEBUG_KMS("win: %d\n", plane->index);
981

982
	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
983 984
		return;

985
	if (plane->index == VP_DEFAULT_WIN)
986
		vp_video_buffer(mixer_ctx, plane);
987
	else
988
		mixer_graph_buffer(mixer_ctx, plane);
989 990
}

991 992
static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
				struct exynos_drm_plane *plane)
993
{
994
	struct mixer_context *mixer_ctx = crtc->ctx;
995 996 997
	struct mixer_resources *res = &mixer_ctx->mixer_res;
	unsigned long flags;

998
	DRM_DEBUG_KMS("win: %d\n", plane->index);
999

1000
	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1001 1002
		return;

1003
	spin_lock_irqsave(&res->reg_slock, flags);
1004
	mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
1005 1006 1007 1008 1009 1010 1011 1012 1013
	spin_unlock_irqrestore(&res->reg_slock, flags);
}

static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
{
	struct mixer_context *mixer_ctx = crtc->ctx;

	if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
		return;
1014 1015

	mixer_vsync_set_update(mixer_ctx, true);
1016
	exynos_crtc_handle_event(crtc);
1017 1018
}

1019
static void mixer_enable(struct exynos_drm_crtc *crtc)
1020
{
1021
	struct mixer_context *ctx = crtc->ctx;
1022 1023
	struct mixer_resources *res = &ctx->mixer_res;

1024
	if (test_bit(MXR_BIT_POWERED, &ctx->flags))
1025 1026
		return;

1027 1028
	pm_runtime_get_sync(ctx->dev);

1029 1030
	exynos_drm_pipe_clk_enable(crtc, true);

1031 1032
	mixer_vsync_set_update(ctx, false);

1033 1034
	mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);

1035
	if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
1036
		mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
1037 1038
		mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
	}
1039
	mixer_win_reset(ctx);
1040

1041 1042
	mixer_vsync_set_update(ctx, true);

1043
	set_bit(MXR_BIT_POWERED, &ctx->flags);
1044 1045
}

1046
static void mixer_disable(struct exynos_drm_crtc *crtc)
1047
{
1048
	struct mixer_context *ctx = crtc->ctx;
1049
	int i;
1050

1051
	if (!test_bit(MXR_BIT_POWERED, &ctx->flags))
1052
		return;
1053

1054
	mixer_stop(ctx);
1055
	mixer_regs_dump(ctx);
1056 1057

	for (i = 0; i < MIXER_WIN_NR; i++)
1058
		mixer_disable_plane(crtc, &ctx->planes[i]);
1059

1060 1061
	exynos_drm_pipe_clk_enable(crtc, false);

1062
	pm_runtime_put(ctx->dev);
1063

1064
	clear_bit(MXR_BIT_POWERED, &ctx->flags);
1065 1066
}

1067
/* Only valid for Mixer version 16.0.33.0 */
1068 1069
static int mixer_atomic_check(struct exynos_drm_crtc *crtc,
		       struct drm_crtc_state *state)
1070
{
1071
	struct drm_display_mode *mode = &state->adjusted_mode;
1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
	u32 w, h;

	w = mode->hdisplay;
	h = mode->vdisplay;

	DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
		mode->hdisplay, mode->vdisplay, mode->vrefresh,
		(mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);

	if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
		(w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
		(w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
		return 0;

	return -EINVAL;
}

1089
static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1090 1091
	.enable			= mixer_enable,
	.disable		= mixer_disable,
1092 1093
	.enable_vblank		= mixer_enable_vblank,
	.disable_vblank		= mixer_disable_vblank,
1094
	.atomic_begin		= mixer_atomic_begin,
1095 1096
	.update_plane		= mixer_update_plane,
	.disable_plane		= mixer_disable_plane,
1097
	.atomic_flush		= mixer_atomic_flush,
1098
	.atomic_check		= mixer_atomic_check,
1099
};
1100

1101
static const struct mixer_drv_data exynos5420_mxr_drv_data = {
1102 1103 1104 1105
	.version = MXR_VER_128_0_0_184,
	.is_vp_enabled = 0,
};

1106
static const struct mixer_drv_data exynos5250_mxr_drv_data = {
1107 1108 1109 1110
	.version = MXR_VER_16_0_33_0,
	.is_vp_enabled = 0,
};

1111
static const struct mixer_drv_data exynos4212_mxr_drv_data = {
1112 1113 1114 1115
	.version = MXR_VER_0_0_0_16,
	.is_vp_enabled = 1,
};

1116
static const struct mixer_drv_data exynos4210_mxr_drv_data = {
1117
	.version = MXR_VER_0_0_0_16,
1118
	.is_vp_enabled = 1,
1119
	.has_sclk = 1,
1120 1121
};

1122
static const struct of_device_id mixer_match_types[] = {
1123
	{
1124 1125 1126 1127 1128 1129
		.compatible = "samsung,exynos4210-mixer",
		.data	= &exynos4210_mxr_drv_data,
	}, {
		.compatible = "samsung,exynos4212-mixer",
		.data	= &exynos4212_mxr_drv_data,
	}, {
1130
		.compatible = "samsung,exynos5-mixer",
1131 1132 1133 1134
		.data	= &exynos5250_mxr_drv_data,
	}, {
		.compatible = "samsung,exynos5250-mixer",
		.data	= &exynos5250_mxr_drv_data,
1135 1136 1137
	}, {
		.compatible = "samsung,exynos5420-mixer",
		.data	= &exynos5420_mxr_drv_data,
1138 1139 1140 1141
	}, {
		/* end node */
	}
};
1142
MODULE_DEVICE_TABLE(of, mixer_match_types);
1143

1144
static int mixer_bind(struct device *dev, struct device *manager, void *data)
1145
{
1146
	struct mixer_context *ctx = dev_get_drvdata(dev);
1147
	struct drm_device *drm_dev = data;
1148
	struct exynos_drm_plane *exynos_plane;
1149
	unsigned int i;
1150
	int ret;
1151

A
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1152 1153 1154 1155
	ret = mixer_initialize(ctx, drm_dev);
	if (ret)
		return ret;

1156
	for (i = 0; i < MIXER_WIN_NR; i++) {
1157 1158
		if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED,
						     &ctx->flags))
1159 1160
			continue;

1161
		ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1162
					&plane_configs[i]);
1163 1164 1165 1166
		if (ret)
			return ret;
	}

1167
	exynos_plane = &ctx->planes[DEFAULT_WIN];
1168
	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1169
			EXYNOS_DISPLAY_TYPE_HDMI, &mixer_crtc_ops, ctx);
1170
	if (IS_ERR(ctx->crtc)) {
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1171
		mixer_ctx_remove(ctx);
1172 1173
		ret = PTR_ERR(ctx->crtc);
		goto free_ctx;
1174
	}
1175 1176

	return 0;
1177 1178 1179 1180

free_ctx:
	devm_kfree(dev, ctx);
	return ret;
1181 1182
}

1183
static void mixer_unbind(struct device *dev, struct device *master, void *data)
1184
{
1185
	struct mixer_context *ctx = dev_get_drvdata(dev);
1186

1187
	mixer_ctx_remove(ctx);
1188 1189 1190 1191 1192 1193 1194 1195 1196
}

static const struct component_ops mixer_component_ops = {
	.bind	= mixer_bind,
	.unbind	= mixer_unbind,
};

static int mixer_probe(struct platform_device *pdev)
{
1197
	struct device *dev = &pdev->dev;
1198
	const struct mixer_drv_data *drv;
1199
	struct mixer_context *ctx;
1200 1201
	int ret;

1202 1203 1204 1205 1206 1207
	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
	if (!ctx) {
		DRM_ERROR("failed to alloc mixer context.\n");
		return -ENOMEM;
	}

1208
	drv = of_device_get_match_data(dev);
1209 1210 1211 1212 1213

	ctx->pdev = pdev;
	ctx->dev = dev;
	ctx->mxr_ver = drv->version;

1214 1215 1216 1217 1218
	if (drv->is_vp_enabled)
		__set_bit(MXR_BIT_VP_ENABLED, &ctx->flags);
	if (drv->has_sclk)
		__set_bit(MXR_BIT_HAS_SCLK, &ctx->flags);

1219 1220
	platform_set_drvdata(pdev, ctx);

1221
	ret = component_add(&pdev->dev, &mixer_component_ops);
1222 1223
	if (!ret)
		pm_runtime_enable(dev);
1224 1225

	return ret;
1226 1227 1228 1229
}

static int mixer_remove(struct platform_device *pdev)
{
1230 1231
	pm_runtime_disable(&pdev->dev);

1232 1233
	component_del(&pdev->dev, &mixer_component_ops);

1234 1235 1236
	return 0;
}

1237
static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1238 1239 1240 1241 1242 1243
{
	struct mixer_context *ctx = dev_get_drvdata(dev);
	struct mixer_resources *res = &ctx->mixer_res;

	clk_disable_unprepare(res->hdmi);
	clk_disable_unprepare(res->mixer);
1244
	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
1245
		clk_disable_unprepare(res->vp);
1246
		if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags))
1247 1248 1249 1250 1251 1252
			clk_disable_unprepare(res->sclk_mixer);
	}

	return 0;
}

1253
static int __maybe_unused exynos_mixer_resume(struct device *dev)
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268
{
	struct mixer_context *ctx = dev_get_drvdata(dev);
	struct mixer_resources *res = &ctx->mixer_res;
	int ret;

	ret = clk_prepare_enable(res->mixer);
	if (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
		return ret;
	}
	ret = clk_prepare_enable(res->hdmi);
	if (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
		return ret;
	}
1269
	if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
1270 1271 1272 1273 1274 1275
		ret = clk_prepare_enable(res->vp);
		if (ret < 0) {
			DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
				  ret);
			return ret;
		}
1276
		if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) {
1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
			ret = clk_prepare_enable(res->sclk_mixer);
			if (ret < 0) {
				DRM_ERROR("Failed to prepare_enable the " \
					   "sclk_mixer clk [%d]\n",
					  ret);
				return ret;
			}
		}
	}

	return 0;
}

static const struct dev_pm_ops exynos_mixer_pm_ops = {
	SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL)
};

1294 1295
struct platform_driver mixer_driver = {
	.driver = {
1296
		.name = "exynos-mixer",
1297
		.owner = THIS_MODULE,
1298
		.pm = &exynos_mixer_pm_ops,
1299
		.of_match_table = mixer_match_types,
1300 1301
	},
	.probe = mixer_probe,
1302
	.remove = mixer_remove,
1303
};