cpufeature.h 6.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11
/*
 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_CPUFEATURE_H
#define __ASM_CPUFEATURE_H

12 13
#include <linux/jump_label.h>

14
#include <asm/hwcap.h>
15
#include <asm/sysreg.h>
16 17 18 19 20 21 22 23 24 25 26

/*
 * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
 * in the kernel and for user space to keep track of which optional features
 * are supported by the current system. So let's map feature 'x' to HWCAP_x.
 * Note that HWCAP_x constants are bit fields so we need to take the log.
 */

#define MAX_CPU_FEATURES	(8 * sizeof(elf_hwcap))
#define cpu_feature(x)		ilog2(HWCAP_ ## x)

27 28
#define ARM64_WORKAROUND_CLEAN_CACHE		0
#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE	1
29
#define ARM64_WORKAROUND_845719			2
30
#define ARM64_HAS_SYSREG_GIC_CPUIF		3
31
#define ARM64_HAS_PAN				4
32
#define ARM64_HAS_LSE_ATOMICS			5
33
#define ARM64_WORKAROUND_CAVIUM_23154		6
34
#define ARM64_WORKAROUND_834220			7
35
#define ARM64_HAS_NO_HW_PREFETCH		8
36
#define ARM64_HAS_UAO				9
37
#define ARM64_ALT_PAN_NOT_UAO			10
38
#define ARM64_HAS_VIRT_HOST_EXTN		11
39
#define ARM64_WORKAROUND_CAVIUM_27456		12
40
#define ARM64_HAS_32BIT_EL0			13
41
#define ARM64_HYP_OFFSET_LOW			14
42

43
#define ARM64_NCAPS				15
44 45

#ifndef __ASSEMBLY__
46

47 48
#include <linux/kernel.h>

49 50 51 52 53 54 55 56 57 58
/* CPU feature register tracking */
enum ftr_type {
	FTR_EXACT,	/* Use a predefined safe value */
	FTR_LOWER_SAFE,	/* Smaller value is safe */
	FTR_HIGHER_SAFE,/* Bigger value is safe */
};

#define FTR_STRICT	true	/* SANITY check strict matching required */
#define FTR_NONSTRICT	false	/* SANITY check ignored */

59 60 61
#define FTR_SIGNED	true	/* Value should be treated as signed */
#define FTR_UNSIGNED	false	/* Value should be treated as unsigned */

62
struct arm64_ftr_bits {
63 64
	bool		sign;	/* Value is signed ? */
	bool		strict;	/* CPU Sanity check: strict matching required ? */
65 66 67
	enum ftr_type	type;
	u8		shift;
	u8		width;
68
	s64		safe_val; /* safe value for FTR_EXACT features */
69 70 71 72 73 74 75 76
};

/*
 * @arm64_ftr_reg - Feature register
 * @strict_mask		Bits which should match across all CPUs for sanity.
 * @sys_val		Safe value across the CPUs (system view)
 */
struct arm64_ftr_reg {
77 78 79 80
	const char			*name;
	u64				strict_mask;
	u64				sys_val;
	const struct arm64_ftr_bits	*ftr_bits;
81 82
};

83 84
extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;

85 86 87 88 89 90
/* scope of capability check */
enum {
	SCOPE_SYSTEM,
	SCOPE_LOCAL_CPU,
};

91 92 93
struct arm64_cpu_capabilities {
	const char *desc;
	u16 capability;
94 95
	int def_scope;			/* default scope */
	bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
96
	void (*enable)(void *);		/* Called on all active CPUs */
97 98 99 100 101
	union {
		struct {	/* To be used for erratum handling only */
			u32 midr_model;
			u32 midr_range_min, midr_range_max;
		};
102 103

		struct {	/* Feature register checking */
104
			u32 sys_reg;
105 106 107 108
			u8 field_pos;
			u8 min_field_value;
			u8 hwcap_type;
			bool sign;
109
			unsigned long hwcap;
110
		};
111 112 113
	};
};

114
extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
115
extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
116

117 118
bool this_cpu_has_cap(unsigned int cap);

119 120 121 122 123
static inline bool cpu_have_feature(unsigned int num)
{
	return elf_hwcap & (1UL << num);
}

124 125
static inline bool cpus_have_cap(unsigned int num)
{
126
	if (num >= ARM64_NCAPS)
127
		return false;
128 129 130 131
	if (__builtin_constant_p(num))
		return static_branch_unlikely(&cpu_hwcap_keys[num]);
	else
		return test_bit(num, cpu_hwcaps);
132 133 134 135
}

static inline void cpus_set_cap(unsigned int num)
{
136
	if (num >= ARM64_NCAPS) {
137
		pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
138
			num, ARM64_NCAPS);
139
	} else {
140
		__set_bit(num, cpu_hwcaps);
141 142
		static_branch_enable(&cpu_hwcap_keys[num]);
	}
143 144
}

145
static inline int __attribute_const__
146
cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
147
{
148 149 150 151
	return (s64)(features << (64 - width - field)) >> (64 - width);
}

static inline int __attribute_const__
152
cpuid_feature_extract_signed_field(u64 features, int field)
153
{
154
	return cpuid_feature_extract_signed_field_width(features, field, 4);
155 156
}

157 158 159 160 161 162 163 164 165 166 167 168
static inline unsigned int __attribute_const__
cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
{
	return (u64)(features << (64 - width - field)) >> (64 - width);
}

static inline unsigned int __attribute_const__
cpuid_feature_extract_unsigned_field(u64 features, int field)
{
	return cpuid_feature_extract_unsigned_field_width(features, field, 4);
}

169
static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
170 171 172 173
{
	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
}

174 175 176 177 178 179 180 181
static inline int __attribute_const__
cpuid_feature_extract_field(u64 features, int field, bool sign)
{
	return (sign) ?
		cpuid_feature_extract_signed_field(features, field) :
		cpuid_feature_extract_unsigned_field(features, field);
}

182
static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
183
{
184
	return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
185 186
}

187
static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
188
{
189 190
	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
191 192
}

193 194 195 196 197 198 199
static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
{
	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);

	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
}

200
void __init setup_cpu_features(void);
201

202
void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
203
			    const char *info);
204
void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
205
void check_local_cpu_errata(void);
206
void __init enable_errata_workarounds(void);
207

208
void verify_local_cpu_errata(void);
209
void verify_local_cpu_capabilities(void);
210

211 212
u64 read_system_reg(u32 id);

213 214 215 216 217
static inline bool cpu_supports_mixed_endian_el0(void)
{
	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
}

218 219 220 221 222
static inline bool system_supports_32bit_el0(void)
{
	return cpus_have_cap(ARM64_HAS_32BIT_EL0);
}

223 224 225 226
static inline bool system_supports_mixed_endian_el0(void)
{
	return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
}
227

228 229
#endif /* __ASSEMBLY__ */

230
#endif