aspm.c 36.5 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
B
Bjorn Helgaas 已提交
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 * Enable PCIe link L0s/L1 state and Clock Power Management
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 *
 * Copyright (C) 2007 Intel
 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/errno.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/delay.h>
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#include <linux/pci-aspm.h>
#include "../pci.h"

#ifdef MODULE_PARAM_PREFIX
#undef MODULE_PARAM_PREFIX
#endif
#define MODULE_PARAM_PREFIX "pcie_aspm."

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/* Note: those are not register definitions */
#define ASPM_STATE_L0S_UP	(1)	/* Upstream direction L0s state */
#define ASPM_STATE_L0S_DW	(2)	/* Downstream direction L0s state */
#define ASPM_STATE_L1		(4)	/* L1 state */
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#define ASPM_STATE_L1_1		(8)	/* ASPM L1.1 state */
#define ASPM_STATE_L1_2		(0x10)	/* ASPM L1.2 state */
#define ASPM_STATE_L1_1_PCIPM	(0x20)	/* PCI PM L1.1 state */
#define ASPM_STATE_L1_2_PCIPM	(0x40)	/* PCI PM L1.2 state */
#define ASPM_STATE_L1_SS_PCIPM	(ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
#define ASPM_STATE_L1_2_MASK	(ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
#define ASPM_STATE_L1SS		(ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
				 ASPM_STATE_L1_2_MASK)
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#define ASPM_STATE_L0S		(ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
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#define ASPM_STATE_ALL		(ASPM_STATE_L0S | ASPM_STATE_L1 |	\
				 ASPM_STATE_L1SS)
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struct aspm_latency {
	u32 l0s;			/* L0s latency (nsec) */
	u32 l1;				/* L1 latency (nsec) */
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};

struct pcie_link_state {
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	struct pci_dev *pdev;		/* Upstream component of the Link */
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	struct pci_dev *downstream;	/* Downstream component, function 0 */
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	struct pcie_link_state *root;	/* pointer to the root port link */
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	struct pcie_link_state *parent;	/* pointer to the parent Link state */
	struct list_head sibling;	/* node in link_list */
	struct list_head children;	/* list of child link states */
	struct list_head link;		/* node in parent's children list */
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	/* ASPM state */
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	u32 aspm_support:7;		/* Supported ASPM state */
	u32 aspm_enabled:7;		/* Enabled ASPM state */
	u32 aspm_capable:7;		/* Capable ASPM state with latency */
	u32 aspm_default:7;		/* Default ASPM state by BIOS */
	u32 aspm_disable:7;		/* Disabled ASPM state */
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	/* Clock PM state */
	u32 clkpm_capable:1;		/* Clock PM capable? */
	u32 clkpm_enabled:1;		/* Current Clock PM state */
	u32 clkpm_default:1;		/* Default Clock PM state by BIOS */

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	/* Exit latencies */
	struct aspm_latency latency_up;	/* Upstream direction exit latency */
	struct aspm_latency latency_dw;	/* Downstream direction exit latency */
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	/*
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	 * Endpoint acceptable latencies. A pcie downstream port only
	 * has one slot under it, so at most there are 8 functions.
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	 */
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	struct aspm_latency acceptable[8];
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	/* L1 PM Substate info */
	struct {
		u32 up_cap_ptr;		/* L1SS cap ptr in upstream dev */
		u32 dw_cap_ptr;		/* L1SS cap ptr in downstream dev */
		u32 ctl1;		/* value to be programmed in ctl1 */
		u32 ctl2;		/* value to be programmed in ctl2 */
	} l1ss;
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};

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static int aspm_disabled, aspm_force;
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static bool aspm_support_enabled = true;
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static DEFINE_MUTEX(aspm_lock);
static LIST_HEAD(link_list);

#define POLICY_DEFAULT 0	/* BIOS default setting */
#define POLICY_PERFORMANCE 1	/* high performance */
#define POLICY_POWERSAVE 2	/* high power saving */
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#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
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#ifdef CONFIG_PCIEASPM_PERFORMANCE
static int aspm_policy = POLICY_PERFORMANCE;
#elif defined CONFIG_PCIEASPM_POWERSAVE
static int aspm_policy = POLICY_POWERSAVE;
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#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
static int aspm_policy = POLICY_POWER_SUPERSAVE;
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#else
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static int aspm_policy;
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#endif

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static const char *policy_str[] = {
	[POLICY_DEFAULT] = "default",
	[POLICY_PERFORMANCE] = "performance",
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	[POLICY_POWERSAVE] = "powersave",
	[POLICY_POWER_SUPERSAVE] = "powersupersave"
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};

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#define LINK_RETRAIN_TIMEOUT HZ

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static int policy_to_aspm_state(struct pcie_link_state *link)
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{
	switch (aspm_policy) {
	case POLICY_PERFORMANCE:
		/* Disable ASPM and Clock PM */
		return 0;
	case POLICY_POWERSAVE:
		/* Enable ASPM L0s/L1 */
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		return (ASPM_STATE_L0S | ASPM_STATE_L1);
	case POLICY_POWER_SUPERSAVE:
		/* Enable Everything */
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		return ASPM_STATE_ALL;
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	case POLICY_DEFAULT:
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		return link->aspm_default;
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	}
	return 0;
}

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static int policy_to_clkpm_state(struct pcie_link_state *link)
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{
	switch (aspm_policy) {
	case POLICY_PERFORMANCE:
		/* Disable ASPM and Clock PM */
		return 0;
	case POLICY_POWERSAVE:
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	case POLICY_POWER_SUPERSAVE:
		/* Enable Clock PM */
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		return 1;
	case POLICY_DEFAULT:
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		return link->clkpm_default;
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	}
	return 0;
}

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static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
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{
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	struct pci_dev *child;
	struct pci_bus *linkbus = link->pdev->subordinate;
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	u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
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	list_for_each_entry(child, &linkbus->devices, bus_list)
		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_CLKREQ_EN,
						   val);
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	link->clkpm_enabled = !!enable;
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}

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static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
{
	/* Don't enable Clock PM if the link is not Clock PM capable */
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	if (!link->clkpm_capable)
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		enable = 0;
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	/* Need nothing if the specified equals to current state */
	if (link->clkpm_enabled == enable)
		return;
	pcie_set_clkpm_nocheck(link, enable);
}

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static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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	int capable = 1, enabled = 1;
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	u32 reg32;
	u16 reg16;
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	struct pci_dev *child;
	struct pci_bus *linkbus = link->pdev->subordinate;
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	/* All functions should have the same cap and state, take the worst */
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	list_for_each_entry(child, &linkbus->devices, bus_list) {
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		pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
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		if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
			capable = 0;
			enabled = 0;
			break;
		}
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		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
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		if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
			enabled = 0;
	}
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	link->clkpm_enabled = enabled;
	link->clkpm_default = enabled;
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	link->clkpm_capable = (blacklist) ? 0 : capable;
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}

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/*
 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
 *   could use common clock. If they are, configure them to use the
 *   common clock. That will reduce the ASPM state exit latency.
 */
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static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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{
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	int same_clock = 1;
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	u16 reg16, parent_reg, child_reg[8];
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	unsigned long start_jiffies;
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	struct pci_dev *child, *parent = link->pdev;
	struct pci_bus *linkbus = parent->subordinate;
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	/*
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	 * All functions of a slot should have the same Slot Clock
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	 * Configuration, so just check one function
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	 */
	child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
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	BUG_ON(!pci_is_pcie(child));
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	/* Check downstream component if bit Slot Clock Configuration is 1 */
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	pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
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	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
		same_clock = 0;

	/* Check upstream component if bit Slot Clock Configuration is 1 */
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	pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
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	if (!(reg16 & PCI_EXP_LNKSTA_SLC))
		same_clock = 0;

	/* Configure downstream component, all functions */
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	list_for_each_entry(child, &linkbus->devices, bus_list) {
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		pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
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		child_reg[PCI_FUNC(child->devfn)] = reg16;
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		if (same_clock)
			reg16 |= PCI_EXP_LNKCTL_CCC;
		else
			reg16 &= ~PCI_EXP_LNKCTL_CCC;
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		pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
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	}

	/* Configure upstream component */
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	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
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	parent_reg = reg16;
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	if (same_clock)
		reg16 |= PCI_EXP_LNKCTL_CCC;
	else
		reg16 &= ~PCI_EXP_LNKCTL_CCC;
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	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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	/* Retrain link */
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	reg16 |= PCI_EXP_LNKCTL_RL;
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	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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	/* Wait for link training end. Break out after waiting for timeout */
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	start_jiffies = jiffies;
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	for (;;) {
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		pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
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		if (!(reg16 & PCI_EXP_LNKSTA_LT))
			break;
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		if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
			break;
		msleep(1);
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	}
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	if (!(reg16 & PCI_EXP_LNKSTA_LT))
		return;

	/* Training failed. Restore common clock configurations */
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	pci_err(parent, "ASPM: Could not configure common clock\n");
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	list_for_each_entry(child, &linkbus->devices, bus_list)
		pcie_capability_write_word(child, PCI_EXP_LNKCTL,
					   child_reg[PCI_FUNC(child->devfn)]);
	pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
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}

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/* Convert L0s latency encoding to ns */
static u32 calc_l0s_latency(u32 encoding)
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{
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	if (encoding == 0x7)
		return (5 * 1000);	/* > 4us */
	return (64 << encoding);
}
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/* Convert L0s acceptable latency encoding to ns */
static u32 calc_l0s_acceptable(u32 encoding)
{
	if (encoding == 0x7)
		return -1U;
	return (64 << encoding);
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}

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/* Convert L1 latency encoding to ns */
static u32 calc_l1_latency(u32 encoding)
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{
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	if (encoding == 0x7)
		return (65 * 1000);	/* > 64us */
	return (1000 << encoding);
}
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/* Convert L1 acceptable latency encoding to ns */
static u32 calc_l1_acceptable(u32 encoding)
{
	if (encoding == 0x7)
		return -1U;
	return (1000 << encoding);
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}

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/* Convert L1SS T_pwr encoding to usec */
static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
{
	switch (scale) {
	case 0:
		return val * 2;
	case 1:
		return val * 10;
	case 2:
		return val * 100;
	}
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	pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
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	return 0;
}

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static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
{
	u64 threshold_ns = threshold_us * 1000;

	/* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
	if (threshold_ns < 32) {
		*scale = 0;
		*value = threshold_ns;
	} else if (threshold_ns < 1024) {
		*scale = 1;
		*value = threshold_ns >> 5;
	} else if (threshold_ns < 32768) {
		*scale = 2;
		*value = threshold_ns >> 10;
	} else if (threshold_ns < 1048576) {
		*scale = 3;
		*value = threshold_ns >> 15;
	} else if (threshold_ns < 33554432) {
		*scale = 4;
		*value = threshold_ns >> 20;
	} else {
		*scale = 5;
		*value = threshold_ns >> 25;
	}
}

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struct aspm_register_info {
	u32 support:2;
	u32 enabled:2;
	u32 latency_encoding_l0s;
	u32 latency_encoding_l1;
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	/* L1 substates */
	u32 l1ss_cap_ptr;
	u32 l1ss_cap;
	u32 l1ss_ctl1;
	u32 l1ss_ctl2;
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};

static void pcie_get_aspm_reg(struct pci_dev *pdev,
			      struct aspm_register_info *info)
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{
	u16 reg16;
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	u32 reg32;
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	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
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	info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
	info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
	info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
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	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
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	info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
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	/* Read L1 PM substate capabilities */
	info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
	info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
	if (!info->l1ss_cap_ptr)
		return;
	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
			      &info->l1ss_cap);
	if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
		info->l1ss_cap = 0;
		return;
	}
	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
			      &info->l1ss_ctl1);
	pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
			      &info->l1ss_ctl2);
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}

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static void pcie_aspm_check_latency(struct pci_dev *endpoint)
{
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	u32 latency, l1_switch_latency = 0;
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	struct aspm_latency *acceptable;
	struct pcie_link_state *link;

	/* Device not in D0 doesn't need latency check */
	if ((endpoint->current_state != PCI_D0) &&
	    (endpoint->current_state != PCI_UNKNOWN))
		return;

	link = endpoint->bus->self->link_state;
	acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];

	while (link) {
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		/* Check upstream direction L0s latency */
		if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
		    (link->latency_up.l0s > acceptable->l0s))
			link->aspm_capable &= ~ASPM_STATE_L0S_UP;

		/* Check downstream direction L0s latency */
		if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
		    (link->latency_dw.l0s > acceptable->l0s))
			link->aspm_capable &= ~ASPM_STATE_L0S_DW;
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		/*
		 * Check L1 latency.
		 * Every switch on the path to root complex need 1
		 * more microsecond for L1. Spec doesn't mention L0s.
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		 *
		 * The exit latencies for L1 substates are not advertised
		 * by a device.  Since the spec also doesn't mention a way
		 * to determine max latencies introduced by enabling L1
		 * substates on the components, it is not clear how to do
		 * a L1 substate exit latency check.  We assume that the
		 * L1 exit latencies advertised by a device include L1
		 * substate latencies (and hence do not do any check).
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		 */
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		latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
		if ((link->aspm_capable & ASPM_STATE_L1) &&
		    (latency + l1_switch_latency > acceptable->l1))
			link->aspm_capable &= ~ASPM_STATE_L1;
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		l1_switch_latency += 1000;

		link = link->parent;
	}
}

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/*
 * The L1 PM substate capability is only implemented in function 0 in a
 * multi function device.
 */
static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
{
	struct pci_dev *child;

	list_for_each_entry(child, &linkbus->devices, bus_list)
		if (PCI_FUNC(child->devfn) == 0)
			return child;
	return NULL;
}

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/* Calculate L1.2 PM substate timing parameters */
static void aspm_calc_l1ss_info(struct pcie_link_state *link,
				struct aspm_register_info *upreg,
				struct aspm_register_info *dwreg)
{
	u32 val1, val2, scale1, scale2;
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	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
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	link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
	link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
	link->l1ss.ctl1 = link->l1ss.ctl2 = 0;

	if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
		return;

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	/* Choose the greater of the two Port Common_Mode_Restore_Times */
	val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
	val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
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	t_common_mode = max(val1, val2);
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	/* Choose the greater of the two Port T_POWER_ON times */
	val1   = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
	scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
	val2   = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
	scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
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	if (calc_l1ss_pwron(link->pdev, scale1, val1) >
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	    calc_l1ss_pwron(link->downstream, scale2, val2)) {
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		link->l1ss.ctl2 |= scale1 | (val1 << 3);
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		t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
	} else {
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		link->l1ss.ctl2 |= scale2 | (val2 << 3);
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		t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
	}

	/*
	 * Set LTR_L1.2_THRESHOLD to the time required to transition the
	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
	 * downstream devices report (via LTR) that they can tolerate at
	 * least that much latency.
	 *
	 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
	 * least 4us.
	 */
	l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
	encode_l12_threshold(l1_2_threshold, &scale, &value);
	link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
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}

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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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	struct pci_dev *child = link->downstream, *parent = link->pdev;
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	struct pci_bus *linkbus = parent->subordinate;
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	struct aspm_register_info upreg, dwreg;
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	if (blacklist) {
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		/* Set enabled/disable so that we will disable ASPM later */
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		link->aspm_enabled = ASPM_STATE_ALL;
		link->aspm_disable = ASPM_STATE_ALL;
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		return;
	}

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	/* Get upstream/downstream components' register state */
	pcie_get_aspm_reg(parent, &upreg);
	pcie_get_aspm_reg(child, &dwreg);

	/*
	 * If ASPM not supported, don't mess with the clocks and link,
	 * bail out now.
	 */
	if (!(upreg.support & dwreg.support))
		return;

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	/* Configure common clock before checking latencies */
	pcie_aspm_configure_common_clock(link);

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	/*
	 * Re-read upstream/downstream components' register state
	 * after clock configuration
	 */
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	pcie_get_aspm_reg(parent, &upreg);
	pcie_get_aspm_reg(child, &dwreg);

	/*
	 * Setup L0s state
	 *
	 * Note that we must not enable L0s in either direction on a
	 * given link unless components on both sides of the link each
	 * support L0s.
	 */
	if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
		link->aspm_support |= ASPM_STATE_L0S;
	if (dwreg.enabled & PCIE_LINK_STATE_L0S)
		link->aspm_enabled |= ASPM_STATE_L0S_UP;
	if (upreg.enabled & PCIE_LINK_STATE_L0S)
		link->aspm_enabled |= ASPM_STATE_L0S_DW;
	link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
	link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);

	/* Setup L1 state */
	if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
		link->aspm_support |= ASPM_STATE_L1;
	if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
		link->aspm_enabled |= ASPM_STATE_L1;
	link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
	link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
559

560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578
	/* Setup L1 substate */
	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
		link->aspm_support |= ASPM_STATE_L1_1;
	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
		link->aspm_support |= ASPM_STATE_L1_2;
	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
	if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;

	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
		link->aspm_enabled |= ASPM_STATE_L1_1;
	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
		link->aspm_enabled |= ASPM_STATE_L1_2;
	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
	if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;

579 580 581
	if (link->aspm_support & ASPM_STATE_L1SS)
		aspm_calc_l1ss_info(link, &upreg, &dwreg);

582 583
	/* Save default state */
	link->aspm_default = link->aspm_enabled;
584 585 586

	/* Setup initial capable state. Will be updated later */
	link->aspm_capable = link->aspm_support;
587 588 589 590 591
	/*
	 * If the downstream component has pci bridge function, don't
	 * do ASPM for now.
	 */
	list_for_each_entry(child, &linkbus->devices, bus_list) {
592
		if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
593
			link->aspm_disable = ASPM_STATE_ALL;
594 595 596
			break;
		}
	}
597

598
	/* Get and check endpoint acceptable latencies */
599
	list_for_each_entry(child, &linkbus->devices, bus_list) {
600
		u32 reg32, encoding;
601
		struct aspm_latency *acceptable =
602
			&link->acceptable[PCI_FUNC(child->devfn)];
603

604 605
		if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
		    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
606 607
			continue;

608
		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
609
		/* Calculate endpoint L0s acceptable latency */
610 611
		encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
		acceptable->l0s = calc_l0s_acceptable(encoding);
612 613 614 615 616
		/* Calculate endpoint L1 acceptable latency */
		encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
		acceptable->l1 = calc_l1_acceptable(encoding);

		pcie_aspm_check_latency(child);
617 618 619
	}
}

620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
				    u32 clear, u32 set)
{
	u32 val;

	pci_read_config_dword(pdev, pos, &val);
	val &= ~clear;
	val |= set;
	pci_write_config_dword(pdev, pos, val);
}

/* Configure the ASPM L1 substates */
static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
{
	u32 val, enable_req;
	struct pci_dev *child = link->downstream, *parent = link->pdev;
	u32 up_cap_ptr = link->l1ss.up_cap_ptr;
	u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;

	enable_req = (link->aspm_enabled ^ state) & state;

	/*
	 * Here are the rules specified in the PCIe spec for enabling L1SS:
	 * - When enabling L1.x, enable bit at parent first, then at child
	 * - When disabling L1.x, disable bit at child first, then at parent
	 * - When enabling ASPM L1.x, need to disable L1
	 *   (at child followed by parent).
	 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
	 *   parameters
	 *
	 * To keep it simple, disable all L1SS bits first, and later enable
	 * what is needed.
	 */

	/* Disable all L1 substates */
	pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
				PCI_L1SS_CTL1_L1SS_MASK, 0);
	pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
				PCI_L1SS_CTL1_L1SS_MASK, 0);
	/*
	 * If needed, disable L1, and it gets enabled later
	 * in pcie_config_aspm_link().
	 */
	if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
		pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_ASPM_L1, 0);
		pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
						   PCI_EXP_LNKCTL_ASPM_L1, 0);
	}

	if (enable_req & ASPM_STATE_L1_2_MASK) {

672
		/* Program T_POWER_ON times in both ports */
673 674 675 676 677
		pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
				       link->l1ss.ctl2);
		pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
				       link->l1ss.ctl2);

678
		/* Program Common_Mode_Restore_Time in upstream device */
679
		pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
680 681
					PCI_L1SS_CTL1_CM_RESTORE_TIME,
					link->l1ss.ctl1);
682

683
		/* Program LTR_L1.2_THRESHOLD time in both ports */
684
		pci_clear_and_set_dword(parent,	up_cap_ptr + PCI_L1SS_CTL1,
685 686 687
					PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
					PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
					link->l1ss.ctl1);
688
		pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
689 690 691
					PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
					PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
					link->l1ss.ctl1);
692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
	}

	val = 0;
	if (state & ASPM_STATE_L1_1)
		val |= PCI_L1SS_CTL1_ASPM_L1_1;
	if (state & ASPM_STATE_L1_2)
		val |= PCI_L1SS_CTL1_ASPM_L1_2;
	if (state & ASPM_STATE_L1_1_PCIPM)
		val |= PCI_L1SS_CTL1_PCIPM_L1_1;
	if (state & ASPM_STATE_L1_2_PCIPM)
		val |= PCI_L1SS_CTL1_PCIPM_L1_2;

	/* Enable what we need to enable */
	pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
				PCI_L1SS_CAP_L1_PM_SS, val);
	pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
				PCI_L1SS_CAP_L1_PM_SS, val);
}

711
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
712
{
713 714
	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
					   PCI_EXP_LNKCTL_ASPMC, val);
715 716
}

717
static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
718
{
719
	u32 upstream = 0, dwstream = 0;
720
	struct pci_dev *child = link->downstream, *parent = link->pdev;
721
	struct pci_bus *linkbus = parent->subordinate;
722

723
	/* Enable only the states that were not explicitly disabled */
724
	state &= (link->aspm_capable & ~link->aspm_disable);
725 726 727 728 729 730 731 732 733 734 735 736

	/* Can't enable any substates if L1 is not enabled */
	if (!(state & ASPM_STATE_L1))
		state &= ~ASPM_STATE_L1SS;

	/* Spec says both ports must be in D0 before enabling PCI PM substates*/
	if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
		state &= ~ASPM_STATE_L1_SS_PCIPM;
		state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
	}

	/* Nothing to do if the link is already in the requested state */
737 738
	if (link->aspm_enabled == state)
		return;
739 740
	/* Convert ASPM state to upstream/downstream ASPM register state */
	if (state & ASPM_STATE_L0S_UP)
741
		dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
742
	if (state & ASPM_STATE_L0S_DW)
743
		upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
744
	if (state & ASPM_STATE_L1) {
745 746
		upstream |= PCI_EXP_LNKCTL_ASPM_L1;
		dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
747
	}
748 749 750 751

	if (link->aspm_capable & ASPM_STATE_L1SS)
		pcie_config_aspm_l1ss(link, state);

752
	/*
753 754 755 756
	 * Spec 2.0 suggests all functions should be configured the
	 * same setting for ASPM. Enabling ASPM L1 should be done in
	 * upstream component first and then downstream, and vice
	 * versa for disabling ASPM L1. Spec doesn't mention L0S.
757
	 */
758 759
	if (state & ASPM_STATE_L1)
		pcie_config_aspm_dev(parent, upstream);
760
	list_for_each_entry(child, &linkbus->devices, bus_list)
761 762 763
		pcie_config_aspm_dev(child, dwstream);
	if (!(state & ASPM_STATE_L1))
		pcie_config_aspm_dev(parent, upstream);
764

765
	link->aspm_enabled = state;
766 767
}

768
static void pcie_config_aspm_path(struct pcie_link_state *link)
769
{
770 771 772
	while (link) {
		pcie_config_aspm_link(link, policy_to_aspm_state(link));
		link = link->parent;
773
	}
774 775
}

776
static void free_link_state(struct pcie_link_state *link)
777
{
778 779
	link->pdev->link_state = NULL;
	kfree(link);
780 781
}

782 783
static int pcie_aspm_sanity_check(struct pci_dev *pdev)
{
784
	struct pci_dev *child;
785
	u32 reg32;
786

787
	/*
788
	 * Some functions in a slot might not all be PCIe functions,
789
	 * very strange. Disable ASPM for the whole slot
790
	 */
791
	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
792
		if (!pci_is_pcie(child))
793
			return -EINVAL;
794 795 796 797 798 799 800 801 802 803

		/*
		 * If ASPM is disabled then we're not going to change
		 * the BIOS state. It's safe to continue even if it's a
		 * pre-1.1 device
		 */

		if (aspm_disabled)
			continue;

804 805 806 807
		/*
		 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
		 * RBER bit to determine if a function is 1.1 version device
		 */
808
		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
809
		if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
810
			pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
811 812
			return -EINVAL;
		}
813 814 815 816
	}
	return 0;
}

817
static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
818 819 820 821 822 823
{
	struct pcie_link_state *link;

	link = kzalloc(sizeof(*link), GFP_KERNEL);
	if (!link)
		return NULL;
824

825 826 827 828
	INIT_LIST_HEAD(&link->sibling);
	INIT_LIST_HEAD(&link->children);
	INIT_LIST_HEAD(&link->link);
	link->pdev = pdev;
829
	link->downstream = pci_function_0(pdev->subordinate);
830 831 832

	/*
	 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
833 834 835 836
	 * hierarchies.  Note that some PCIe host implementations omit
	 * the root ports entirely, in which case a downstream port on
	 * a switch may become the root of the link state chain for all
	 * its subordinate endpoints.
837 838
	 */
	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
839 840
	    pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
	    !pdev->bus->parent->self) {
841 842
		link->root = link;
	} else {
843
		struct pcie_link_state *parent;
844

845 846 847 848 849
		parent = pdev->bus->parent->self->link_state;
		if (!parent) {
			kfree(link);
			return NULL;
		}
850

851
		link->parent = parent;
852
		link->root = link->parent->root;
853 854
		list_add(&link->link, &parent->children);
	}
855

856 857 858 859 860
	list_add(&link->sibling, &link_list);
	pdev->link_state = link;
	return link;
}

861 862
/*
 * pcie_aspm_init_link_state: Initiate PCI express link state.
863
 * It is called after the pcie and its children devices are scanned.
864 865 866 867
 * @pdev: the root port or switch downstream port
 */
void pcie_aspm_init_link_state(struct pci_dev *pdev)
{
868
	struct pcie_link_state *link;
869
	int blacklist = !!pcie_aspm_sanity_check(pdev);
870

871 872 873
	if (!aspm_support_enabled)
		return;

874
	if (pdev->link_state)
875
		return;
876 877 878 879 880 881 882

	/*
	 * We allocate pcie_link_state for the component on the upstream
	 * end of a Link, so there's nothing to do unless this device has a
	 * Link on its secondary side.
	 */
	if (!pdev->has_secondary_link)
883
		return;
884

885
	/* VIA has a strange chipset, root port is under a bridge */
886
	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
887
	    pdev->bus->self)
888
		return;
889

890 891 892 893 894
	down_read(&pci_bus_sem);
	if (list_empty(&pdev->subordinate->devices))
		goto out;

	mutex_lock(&aspm_lock);
895
	link = alloc_pcie_link_state(pdev);
896 897 898
	if (!link)
		goto unlock;
	/*
899 900 901
	 * Setup initial ASPM state. Note that we need to configure
	 * upstream links also because capable state of them can be
	 * update through pcie_aspm_cap_init().
902
	 */
903
	pcie_aspm_cap_init(link, blacklist);
904

905
	/* Setup initial Clock PM state */
906
	pcie_clkpm_cap_init(link, blacklist);
907 908 909 910 911 912 913 914 915

	/*
	 * At this stage drivers haven't had an opportunity to change the
	 * link policy setting. Enabling ASPM on broken hardware can cripple
	 * it even before the driver has had a chance to disable ASPM, so
	 * default to a safe level right now. If we're enabling ASPM beyond
	 * the BIOS's expectation, we'll do so once pci_enable_device() is
	 * called.
	 */
916 917
	if (aspm_policy != POLICY_POWERSAVE &&
	    aspm_policy != POLICY_POWER_SUPERSAVE) {
918 919 920 921
		pcie_config_aspm_path(link);
		pcie_set_clkpm(link, policy_to_clkpm_state(link));
	}

922
unlock:
923 924 925 926 927
	mutex_unlock(&aspm_lock);
out:
	up_read(&pci_bus_sem);
}

928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
/* Recheck latencies and update aspm_capable for links under the root */
static void pcie_update_aspm_capable(struct pcie_link_state *root)
{
	struct pcie_link_state *link;
	BUG_ON(root->parent);
	list_for_each_entry(link, &link_list, sibling) {
		if (link->root != root)
			continue;
		link->aspm_capable = link->aspm_support;
	}
	list_for_each_entry(link, &link_list, sibling) {
		struct pci_dev *child;
		struct pci_bus *linkbus = link->pdev->subordinate;
		if (link->root != root)
			continue;
		list_for_each_entry(child, &linkbus->devices, bus_list) {
944 945
			if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
			    (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
946 947 948 949 950 951
				continue;
			pcie_aspm_check_latency(child);
		}
	}
}

952 953 954 955
/* @pdev: the endpoint device */
void pcie_aspm_exit_link_state(struct pci_dev *pdev)
{
	struct pci_dev *parent = pdev->bus->self;
956
	struct pcie_link_state *link, *root, *parent_link;
957

958
	if (!parent || !parent->link_state)
959
		return;
960

961 962 963 964
	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
	/*
	 * All PCIe functions are in one slot, remove one function will remove
965
	 * the whole slot, so just wait until we are the last function left.
966
	 */
967
	if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
968 969
		goto out;

970
	link = parent->link_state;
971
	root = link->root;
972
	parent_link = link->parent;
973

974
	/* All functions are removed, so just disable ASPM for the link */
975
	pcie_config_aspm_link(link, 0);
976 977
	list_del(&link->sibling);
	list_del(&link->link);
978
	/* Clock PM is for endpoint device */
979
	free_link_state(link);
980 981

	/* Recheck latencies and configure upstream links */
982 983 984 985
	if (parent_link) {
		pcie_update_aspm_capable(root);
		pcie_config_aspm_path(parent_link);
	}
986 987 988 989 990 991 992 993
out:
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);
}

/* @pdev: the root port or switch downstream port */
void pcie_aspm_pm_state_change(struct pci_dev *pdev)
{
994
	struct pcie_link_state *link = pdev->link_state;
995

996
	if (aspm_disabled || !link)
997 998
		return;
	/*
999 1000
	 * Devices changed PM state, we should recheck if latency
	 * meets all functions' requirement
1001
	 */
1002 1003 1004
	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
	pcie_update_aspm_capable(link->root);
1005
	pcie_config_aspm_path(link);
1006 1007
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);
1008 1009
}

1010 1011 1012 1013
void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
{
	struct pcie_link_state *link = pdev->link_state;

1014
	if (aspm_disabled || !link)
1015 1016
		return;

1017 1018
	if (aspm_policy != POLICY_POWERSAVE &&
	    aspm_policy != POLICY_POWER_SUPERSAVE)
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028
		return;

	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
	pcie_config_aspm_path(link);
	pcie_set_clkpm(link, policy_to_clkpm_state(link));
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);
}

1029
static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1030 1031
{
	struct pci_dev *parent = pdev->bus->self;
1032
	struct pcie_link_state *link;
1033

1034
	if (!pci_is_pcie(pdev))
1035
		return;
1036

1037
	if (pdev->has_secondary_link)
1038 1039 1040 1041
		parent = pdev;
	if (!parent || !parent->link_state)
		return;

1042 1043 1044 1045 1046 1047 1048 1049
	/*
	 * A driver requested that ASPM be disabled on this device, but
	 * if we don't have permission to manage ASPM (e.g., on ACPI
	 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
	 * the _OSC method), we can't honor that request.  Windows has
	 * a similar mechanism using "PciASPMOptOut", which is also
	 * ignored in this situation.
	 */
1050
	if (aspm_disabled) {
1051
		pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1052 1053 1054
		return;
	}

1055 1056
	if (sem)
		down_read(&pci_bus_sem);
1057
	mutex_lock(&aspm_lock);
1058
	link = parent->link_state;
1059 1060 1061 1062
	if (state & PCIE_LINK_STATE_L0S)
		link->aspm_disable |= ASPM_STATE_L0S;
	if (state & PCIE_LINK_STATE_L1)
		link->aspm_disable |= ASPM_STATE_L1;
1063 1064
	pcie_config_aspm_link(link, policy_to_aspm_state(link));

1065
	if (state & PCIE_LINK_STATE_CLKPM) {
1066 1067
		link->clkpm_capable = 0;
		pcie_set_clkpm(link, 0);
1068
	}
1069
	mutex_unlock(&aspm_lock);
1070 1071 1072 1073 1074 1075
	if (sem)
		up_read(&pci_bus_sem);
}

void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
{
1076
	__pci_disable_link_state(pdev, state, false);
1077 1078 1079
}
EXPORT_SYMBOL(pci_disable_link_state_locked);

1080 1081 1082 1083 1084 1085 1086 1087 1088
/**
 * pci_disable_link_state - Disable device's link state, so the link will
 * never enter specific states.  Note that if the BIOS didn't grant ASPM
 * control to the OS, this does nothing because we can't touch the LNKCTL
 * register.
 *
 * @pdev: PCI device
 * @state: ASPM link state to disable
 */
1089 1090
void pci_disable_link_state(struct pci_dev *pdev, int state)
{
1091
	__pci_disable_link_state(pdev, state, true);
1092 1093 1094
}
EXPORT_SYMBOL(pci_disable_link_state);

1095 1096
static int pcie_aspm_set_policy(const char *val,
				const struct kernel_param *kp)
1097 1098
{
	int i;
1099
	struct pcie_link_state *link;
1100

1101 1102
	if (aspm_disabled)
		return -EPERM;
1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113
	for (i = 0; i < ARRAY_SIZE(policy_str); i++)
		if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
			break;
	if (i >= ARRAY_SIZE(policy_str))
		return -EINVAL;
	if (i == aspm_policy)
		return 0;

	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
	aspm_policy = i;
1114 1115 1116
	list_for_each_entry(link, &link_list, sibling) {
		pcie_config_aspm_link(link, policy_to_aspm_state(link));
		pcie_set_clkpm(link, policy_to_clkpm_state(link));
1117 1118 1119 1120 1121 1122
	}
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);
	return 0;
}

1123
static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
{
	int i, cnt = 0;
	for (i = 0; i < ARRAY_SIZE(policy_str); i++)
		if (i == aspm_policy)
			cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
		else
			cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
	return cnt;
}

module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
	NULL, 0644);

#ifdef CONFIG_PCIEASPM_DEBUG
static ssize_t link_state_show(struct device *dev,
		struct device_attribute *attr,
		char *buf)
{
	struct pci_dev *pci_device = to_pci_dev(dev);
	struct pcie_link_state *link_state = pci_device->link_state;

1145
	return sprintf(buf, "%d\n", link_state->aspm_enabled);
1146 1147 1148 1149 1150 1151 1152
}

static ssize_t link_state_store(struct device *dev,
		struct device_attribute *attr,
		const char *buf,
		size_t n)
{
1153
	struct pci_dev *pdev = to_pci_dev(dev);
1154
	struct pcie_link_state *link, *root = pdev->link_state->root;
1155
	u32 state;
1156

1157 1158
	if (aspm_disabled)
		return -EPERM;
1159

1160 1161 1162 1163
	if (kstrtouint(buf, 10, &state))
		return -EINVAL;
	if ((state & ~ASPM_STATE_ALL) != 0)
		return -EINVAL;
1164

1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
	list_for_each_entry(link, &link_list, sibling) {
		if (link->root != root)
			continue;
		pcie_config_aspm_link(link, state);
	}
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);
	return n;
1175 1176 1177 1178 1179 1180 1181 1182 1183
}

static ssize_t clk_ctl_show(struct device *dev,
		struct device_attribute *attr,
		char *buf)
{
	struct pci_dev *pci_device = to_pci_dev(dev);
	struct pcie_link_state *link_state = pci_device->link_state;

1184
	return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1185 1186 1187 1188 1189 1190 1191
}

static ssize_t clk_ctl_store(struct device *dev,
		struct device_attribute *attr,
		const char *buf,
		size_t n)
{
1192
	struct pci_dev *pdev = to_pci_dev(dev);
1193
	bool state;
1194

1195
	if (strtobool(buf, &state))
1196 1197 1198 1199
		return -EINVAL;

	down_read(&pci_bus_sem);
	mutex_lock(&aspm_lock);
1200
	pcie_set_clkpm_nocheck(pdev->link_state, state);
1201 1202 1203 1204 1205 1206
	mutex_unlock(&aspm_lock);
	up_read(&pci_bus_sem);

	return n;
}

1207 1208
static DEVICE_ATTR_RW(link_state);
static DEVICE_ATTR_RW(clk_ctl);
1209 1210 1211 1212 1213 1214

static char power_group[] = "power";
void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
{
	struct pcie_link_state *link_state = pdev->link_state;

1215
	if (!link_state)
1216 1217
		return;

1218
	if (link_state->aspm_support)
1219 1220
		sysfs_add_file_to_group(&pdev->dev.kobj,
			&dev_attr_link_state.attr, power_group);
1221
	if (link_state->clkpm_capable)
1222 1223 1224 1225 1226 1227 1228 1229
		sysfs_add_file_to_group(&pdev->dev.kobj,
			&dev_attr_clk_ctl.attr, power_group);
}

void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
{
	struct pcie_link_state *link_state = pdev->link_state;

1230
	if (!link_state)
1231 1232
		return;

1233
	if (link_state->aspm_support)
1234 1235
		sysfs_remove_file_from_group(&pdev->dev.kobj,
			&dev_attr_link_state.attr, power_group);
1236
	if (link_state->clkpm_capable)
1237 1238 1239 1240 1241 1242 1243
		sysfs_remove_file_from_group(&pdev->dev.kobj,
			&dev_attr_clk_ctl.attr, power_group);
}
#endif

static int __init pcie_aspm_disable(char *str)
{
1244
	if (!strcmp(str, "off")) {
1245
		aspm_policy = POLICY_DEFAULT;
1246
		aspm_disabled = 1;
1247
		aspm_support_enabled = false;
1248 1249 1250
		printk(KERN_INFO "PCIe ASPM is disabled\n");
	} else if (!strcmp(str, "force")) {
		aspm_force = 1;
1251
		printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1252
	}
1253 1254 1255
	return 1;
}

1256
__setup("pcie_aspm=", pcie_aspm_disable);
1257

1258 1259
void pcie_no_aspm(void)
{
1260 1261 1262 1263 1264 1265 1266 1267
	/*
	 * Disabling ASPM is intended to prevent the kernel from modifying
	 * existing hardware state, not to clear existing state. To that end:
	 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
	 * (b) prevent userspace from changing policy
	 */
	if (!aspm_force) {
		aspm_policy = POLICY_DEFAULT;
1268
		aspm_disabled = 1;
1269
	}
1270 1271
}

1272 1273 1274 1275 1276
bool pcie_aspm_support_enabled(void)
{
	return aspm_support_enabled;
}
EXPORT_SYMBOL(pcie_aspm_support_enabled);
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